Abstract: A memory module includes memory devices and a power tracker for monitoring power consumption by the memory devices. The power tracker generates digital power consumption data that can be stored and used to anticipate and/or diagnose of power-related problems. The invention allows accurate monitoring of conditions that could otherwise lead to failure and provides a source of diagnostic data in the event of system failure related to excessive power consumption. Modules that self-monitor power consumption can provide highly accurate data to the user and/or the system, which has significant advantages over error-prone theoretical measurements or estimations.

Abstract: A processor module includes an execution unit and a power monitor for monitoring power consumption by processor components including said execution unit.

Abstract: A computer system uses power-consumption monitors for each of plural sets of devices. A power budget arbiter determines whether a collective power-consumption criterion is met at least in part as a function of said power-consumption data.

Abstract: An interface module for interfacing an external device with a host computer is physically and electrically connected to the host computer. The module monitors its own power consumption and reports its power consumption to the host computer. This information can be used to determine the total power consumed by multiple modules, to indicate a problem with the interface module, or to detect a leakage current associated with the external device when main power is off.

Abstract: A server computer system receives error data including a physical memory address along with configuration data associated with the physical memory address, and may also include error syndrome data. The server computer system includes a memory error decoder component that is operable to process the physical memory address and configuration data to generate a memory bus address corresponding to the physical memory address. The memory error decoder also processes the error syndrome data to generate the location of an erroneous bit within a group of data bits and all possible electrical routes of the erroneous data bit within a failing computer system. The server system outputs the memory bus address and the location and electrical route of the erroneous data bit.

Abstract: A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches coupled to memory module interfaces. The branches have respective lengths between the branch point and the memory module interfaces to be configured symmetrically, wherein the branch point is at a point to balance signal transmission on the branches.

Abstract: A double-high memory system compatible with termination schemes for single-high memory systems. The system includes an interface for input and output of data. A plurality of memory units is configured in two rows. A transmission line couples the plurality of memory units and the interface. The double-high memory system is provided in a non-stacked arrangement.