Patents by Inventor Derek T. Bachand

Derek T. Bachand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10133670
    Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Ramadass Nagarajan, Jose S. Niell, Michael T. Klinglesmith, Derek T. Bachand, Ganesh Kumar
  • Publication number: 20160188469
    Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 30, 2016
    Inventors: Ramadass Nagarajan, Jose S. Niell, Michael T. Klinglesmith, Derek T. Bachand, Ganesh Kumar
  • Patent number: 8122194
    Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Chinna Prudvi, Derek T. Bachand
  • Publication number: 20100037027
    Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
    Type: Application
    Filed: May 19, 2009
    Publication date: February 11, 2010
    Inventors: Chinna Prudvi, Derek T. Bachand
  • Patent number: 7555603
    Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Chinna Prudvi, Derek T. Bachand
  • Patent number: 7487305
    Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: David L. Hill, Derek T. Bachand
  • Patent number: 7143242
    Abstract: A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: November 28, 2006
    Assignee: Intel Corporation
    Inventors: David L. Hill, Derek T. Bachand, Chinna B. Prudvi, Deborah T. Marr
  • Patent number: 7133981
    Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: David L Hill, Derek T. Bachand
  • Patent number: 6782457
    Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: David L Hill, Derek T. Bachand
  • Patent number: 6735675
    Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
  • Patent number: 6732242
    Abstract: A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests and write requests. The controller posts at least one write request to an external bus every defined number of transactions if at least one non-posted write request is stored in the queue registers.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: David L. Hill, Paul D. Breuder, Robert J. Greiner, Derek T. Bachand
  • Publication number: 20040059854
    Abstract: A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 25, 2004
    Inventors: David L. Hill, Derek T. Bachand, Chinna B. Prudvi, Deborah T. Marr
  • Patent number: 6668309
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Patent number: 6654837
    Abstract: A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: November 25, 2003
    Assignee: Intel Corporation
    Inventors: David L. Hill, Derek T. Bachand, Chinna B. Prudvi, Deborah T. Marr
  • Publication number: 20030196050
    Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
    Type: Application
    Filed: June 5, 2003
    Publication date: October 16, 2003
    Inventors: David L. Hill, Derek T. Bachand
  • Publication number: 20030188107
    Abstract: A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests and write requests. The controller posts at least one write request to an external bus every defined number of transactions if at least one non-posted write request is stored in the queue registers.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 2, 2003
    Inventors: David L. Hill, Paul D. Breuder, Robert J. Greiner, Derek T. Bachand
  • Patent number: 6606692
    Abstract: A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: David L Hill, Derek T. Bachand
  • Publication number: 20030115424
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Application
    Filed: January 29, 2003
    Publication date: June 19, 2003
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch
  • Publication number: 20030110359
    Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.
    Type: Application
    Filed: January 17, 2003
    Publication date: June 12, 2003
    Inventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
  • Patent number: 6578116
    Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: June 10, 2003
    Assignee: Intel Corporation
    Inventors: Derek T. Bachand, Paul Breuder, Matthew A. Fisch