Patents by Inventor Derek Tao
Derek Tao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9978446Abstract: A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.Type: GrantFiled: December 14, 2016Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) Hsu, Yukit Tang, Derek Tao, Young Seog Kim
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Publication number: 20170092353Abstract: A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.Type: ApplicationFiled: December 14, 2016Publication date: March 30, 2017Inventors: Kuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
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Patent number: 9530487Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.Type: GrantFiled: December 17, 2015Date of Patent: December 27, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) Hsu, Yukit Tang, Derek Tao, Young Seog Kim
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Publication number: 20160104525Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.Type: ApplicationFiled: December 17, 2015Publication date: April 14, 2016Inventors: Kuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
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Patent number: 9218857Abstract: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.Type: GrantFiled: October 11, 2013Date of Patent: December 22, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) Hsu, Yukit Tang, Derek Tao, Young Seog Kim
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Patent number: 8743581Abstract: A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage.Type: GrantFiled: February 13, 2013Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yukit Tang, Kuoyuan Hsu, Derek Tao
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Publication number: 20140043921Abstract: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.Type: ApplicationFiled: October 11, 2013Publication date: February 13, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
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Patent number: 8576611Abstract: Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.Type: GrantFiled: July 8, 2010Date of Patent: November 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuoyuan (Peter) Hsu, Yukit Tang, Derek Tao, Young Seog Kim
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Patent number: 8400804Abstract: A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage.Type: GrantFiled: August 30, 2010Date of Patent: March 19, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yukit Tang, Kuoyuan Hsu, Derek Tao
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Patent number: 8395960Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers.Type: GrantFiled: May 12, 2010Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek Tao
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Patent number: 8270241Abstract: An embodiment of the invention is related to a memory that includes a memory array having a plurality of memory banks, each of which includes a plurality of rows and a plurality of columns of memory cells. Each memory column includes a switch circuit providing a first voltage and a second voltage to memory cells in the column and to the pre-charge circuit associated with the column. In an application, at one particular point in time (e.g., an accessed cycle), only one column in a memory bank uses the operating voltage Ovoltage while the other N?1 columns in the same memory bank use the retention voltage Rvoltage. Other embodiments are also disclosed.Type: GrantFiled: February 16, 2010Date of Patent: September 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Derek Tao
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Publication number: 20120051112Abstract: A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage.Type: ApplicationFiled: August 30, 2010Publication date: March 1, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yukit TANG, Kuoyuan HSU, Derek TAO
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Publication number: 20120008376Abstract: Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.Type: ApplicationFiled: July 8, 2010Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
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Publication number: 20110280095Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek TAO
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Publication number: 20110199846Abstract: An embodiment of the invention is related to a memory that includes a memory array having a plurality of memory banks, each of which includes a plurality of rows and a plurality of columns of memory cells. Each memory column includes a switch circuit providing a first voltage and a second voltage to memory cells in the column and to the pre-charge circuit associated with the column. In an application, at one particular point in time (e.g., an accessed cycle), only one column in a memory bank uses the operating voltage Ovoltage while the other N?1 columns in the same memory bank use the retention voltage Rvoltage. Other embodiments are also disclosed.Type: ApplicationFiled: February 16, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Derek TAO
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Patent number: 7782692Abstract: A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.Type: GrantFiled: January 9, 2008Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Derek Tao, Jay Lu, Annie Lum
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Patent number: 7663959Abstract: A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected.Type: GrantFiled: May 12, 2008Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Derek Tao, Chungjz Lu, Annie-Li-Keow Lum
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Publication number: 20090175099Abstract: A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Derek Tao, Jay Lu, Annie Lum
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Publication number: 20090141579Abstract: A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected.Type: ApplicationFiled: May 12, 2008Publication date: June 4, 2009Inventors: Derek Tao, Chungjz Lu, Annie-Li-Keow Lum
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Patent number: 6285590Abstract: A low power consumption semiconductor memory circuit that includes a memory core (e.g., a ROM core) with a plurality of intersecting bit lines and word lines, as well as a plurality of memory cells at predetermined intersections of the bit and word lines. The low power consumption semiconductor memory circuit also includes a pre-discharge circuit, a multiplexer circuit (MUX), and a sense amplifier circuit. The pre-discharge circuit is electrically connected to the memory core and configured for discharging each of the bit lines to ground (GND). The MUX circuit is electrically connected to the pre-discharge circuit and configured for selecting at least one of the bit lines as its input. Furthermore, the sense amplifier circuit is configured for sensing an electrical state of an output node of the MUX circuit and, in one embodiment, includes a current generator circuit configured to charge a pre-discharged bit line during a READ operation.Type: GrantFiled: June 28, 2000Date of Patent: September 4, 2001Assignee: National Semiconductor CorporationInventors: Pavel Poplevine, Jasopin Lee, Derek Tao