Abstract: Each column of pixels in an image sensor array has at least two column bitlines connected to an output of each pixel. A readout input circuit includes first inputs and a second input. Each first input is connected, via a capacitance, to a comparator input node. The second input is connected via a capacitance to the same comparator input node. The first inputs receive, in parallel, an analog signal acquired from the pixels via the column bitlines. The analog signals vary during a pixel readout period and have a first level during a first calibration period and a second level during a second read period with the analog signals being constantly read onto the capacitances during both the first calibration period and the second read period. The comparator compares an average of the signals on the plurality of first inputs to the reference signal.

Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.

Abstract: Each column of pixels in an image sensor array has at least two column bitlines connected to an output of each pixel. A readout input circuit includes first inputs and a second input. Each first input is connected, via a capacitance, to a comparator input node. The second input is connected via a capacitance to the same comparator input node. The first inputs receive, in parallel, an analog signal acquired from the pixels via the column bitlines. The analog signals vary during a pixel readout period and have a first level during a first calibration period and a second level during a second read period with the analog signals being constantly read onto the capacitances during both the first calibration period and the second read period. The comparator compares an average of the signals on the plurality of first inputs to the reference signal.

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.

Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.