Patents by Inventor Derek W. Robinson
Derek W. Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10050157Abstract: A rectifying diode. The diode comprises a first conductor region and a second conductor region. The diode further comprises a diode conductive path between the first conductor region and the second conductor region. The path comprises a first semiconductor volume having a non-uniform distribution of ions and a second semiconductor volume having a uniform distribution of ions relative to the first semiconductor volume.Type: GrantFiled: July 1, 2005Date of Patent: August 14, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vladimir F. Drobny, Derek W. Robinson
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Patent number: 9721849Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.Type: GrantFiled: September 2, 2016Date of Patent: August 1, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Derek W. Robinson, Amitava Chatterjee
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Publication number: 20160372376Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Derek W. ROBINSON, Amitava CHATTERJEE
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Patent number: 9461035Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.Type: GrantFiled: December 19, 2013Date of Patent: October 4, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Derek W. Robinson, Amitava Chatterjee
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Publication number: 20140183655Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.Type: ApplicationFiled: December 19, 2013Publication date: July 3, 2014Applicant: Texas Instruments IncorporatedInventors: Derek W. ROBINSON, Amitava CHATTERJEE
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Patent number: 8030155Abstract: A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.Type: GrantFiled: May 12, 2008Date of Patent: October 4, 2011Assignee: Texas Instruments IncorporatedInventors: Vladimir F. Drobny, Derek W. Robinson
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Patent number: 7964919Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.Type: GrantFiled: July 21, 2008Date of Patent: June 21, 2011Assignee: Texas Instruments IncorporatedInventors: Eric W. Beach, Vladimir F. Drobny, Derek W. Robinson
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Publication number: 20080272460Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.Type: ApplicationFiled: July 21, 2008Publication date: November 6, 2008Inventors: Eric W. Beach, Vladimir F. Drobny, Derek W. Robinson
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Publication number: 20080213955Abstract: A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.Type: ApplicationFiled: May 12, 2008Publication date: September 4, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Vladimir F. Drobny, Derek W. Robinson
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Patent number: 7416951Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.Type: GrantFiled: September 29, 2005Date of Patent: August 26, 2008Assignee: Texas Instruments IncorporatedInventors: Eric W. Beach, Vladimir F. Drobny, Derek W. Robinson
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Patent number: 7202533Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.Type: GrantFiled: September 29, 2005Date of Patent: April 10, 2007Assignee: Texas Instruments IncorporatedInventors: Eric W. Beach, Vladimir F. Drobny, Derek W. Robinson
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Patent number: 5541120Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filler with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optical cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.Type: GrantFiled: November 9, 1994Date of Patent: July 30, 1996Assignee: Analog Devices, Inc.Inventors: Derek W. Robinson, William A. Krieger, Andre M. Martinez, Marion R. McDevitt
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Patent number: 5444285Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.Type: GrantFiled: November 9, 1994Date of Patent: August 22, 1995Assignee: Analog Devices, Inc.Inventors: Derek W. Robinson, William A. Krieger, Andre M. Martinez, Marion R. McDevitt
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Patent number: 5409845Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.Type: GrantFiled: September 10, 1993Date of Patent: April 25, 1995Assignee: Analog Devices, Inc.Inventors: Derek W. Robinson, William A. Krieger, Andre M. Martinez, Marion R. McDevitt