Abstract: In various examples, three-dimensional (3D) object or feature detection and localization for autonomous and semi-autonomous systems and applications is described herein. Systems and methods are disclosed that use different types of sensors, such as an image sensor and a LIDAR sensor, to determine information associated with objects, such as traffic objects (e.g., traffic signs, traffic signals, traffic markings, etc.). To determine the information for an object, image data is processed to determine a bounding shape associated with the object. The bounding shape is then used to determine a 3D shape, such as a frustum, corresponding to the object. Additionally, points data generated using the LIDAR sensor, such as an occupancy map and/or a point cloud, is processed to identify a portion of the points associated with (e.g., located within) the 3D shape. This portion of the points may then be used to determine the information associated with the object.

Abstract: In various examples, three-dimensional (3D) object or feature detection and localization for autonomous and semi-autonomous systems and applications is described herein. Systems and methods are disclosed that use different types of sensors, such as an image sensor and a LIDAR sensor, to determine information associated with objects, such as traffic objects (e.g., traffic signs, traffic signals, traffic markings, etc.). To determine the information for an object, image data is processed to determine a bounding shape associated with the object. The bounding shape is then used to determine a 3D shape, such as a frustum, corresponding to the object. Additionally, points data generated using the LIDAR sensor, such as an occupancy map and/or a point cloud, is processed to identify a portion of the points associated with (e.g., located within) the 3D shape. This portion of the points may then be used to determine the information associated with the object.

Abstract: A replica column for bit line tracking of a bitcell array is disclosed that includes just one replica access transistor for each row in the bitcell array. If there are N rows, there are thus N replica access transistors in the replica column, where N is a plural positive integer. The replica column includes no other transistors besides the replica access transistors.

Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

Abstract: A wave-driven electronic candle includes an illuminator, a power supply for providing the necessary working voltage, a signal receiver, and a controller including a signal amplifier for amplifying a wave signal received by the signal receiver, a signal regulator for selecting a series or part of the waveform from the signal amplified by the signal amplifier, a filter for removing noises from the selected waveform, and an output amplifier for amplifying the filtered waveform signal for output to the illuminator to control the illuminator to flash.

Abstract: An electronic candle includes a power source, and two circuit assemblies electrically coupled to the power source in parallel and respectively including a waveform generator, a drive circuit and a first light-emitting diode being electrically connected in series. By means of controlling the two waveform generators to respectively generate a triangle wave, square wave, T wave or sawtooth wave, synchronously or asynchronously, the electronic candle simulates the flashing candlelight of a real wax candle.

Abstract: An electronic candle includes a power source, and two circuit assemblies electrically coupled to the power source in parallel and respectively including a waveform generator, a drive circuit and a first light-emitting diode being electrically connected in series. By means of controlling the two waveform generators to respectively generate a triangle wave, square wave, T wave or sawtooth wave, synchronously or asynchronously, the electronic candle simulates the flashing candlelight of a real wax candle.

Abstract: A moistureless cooling device used in a mobile refrigerator is disclosed to include a thermal-insulation container having a storage chamber defined therein for storing low temperature substances and an opening in communication with the storage chamber and covered by a container cover, an air heat exchanger unit having a flow-guide conduit extending through and isolated from the storage chamber, and an air supply unit installed in one of the air inlet and air outlet of the flow-guide conduit for delivering outside air through the flow-guide conduit to transfer low temperature from the low temperature substances in the storage chamber of the thermal-insulation container to an enclosed space in the mobile refrigerator.