Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

Abstract: A wave-driven electronic candle includes an illuminator, a power supply for providing the necessary working voltage, a signal receiver, and a controller including a signal amplifier for amplifying a wave signal received by the signal receiver, a signal regulator for selecting a series or part of the waveform from the signal amplified by the signal amplifier, a filter for removing noises from the selected waveform, and an output amplifier for amplifying the filtered waveform signal for output to the illuminator to control the illuminator to flash.

Abstract: An electronic candle includes a power source, and two circuit assemblies electrically coupled to the power source in parallel and respectively including a waveform generator, a drive circuit and a first light-emitting diode being electrically connected in series. By means of controlling the two waveform generators to respectively generate a triangle wave, square wave, T wave or sawtooth wave, synchronously or asynchronously, the electronic candle simulates the flashing candlelight of a real wax candle.

Abstract: An electronic candle includes a power source, and two circuit assemblies electrically coupled to the power source in parallel and respectively including a waveform generator, a drive circuit and a first light-emitting diode being electrically connected in series. By means of controlling the two waveform generators to respectively generate a triangle wave, square wave, T wave or sawtooth wave, synchronously or asynchronously, the electronic candle simulates the flashing candlelight of a real wax candle.

Abstract: A moistureless cooling device used in a mobile refrigerator is disclosed to include a thermal-insulation container having a storage chamber defined therein for storing low temperature substances and an opening in communication with the storage chamber and covered by a container cover, an air heat exchanger unit having a flow-guide conduit extending through and isolated from the storage chamber, and an air supply unit installed in one of the air inlet and air outlet of the flow-guide conduit for delivering outside air through the flow-guide conduit to transfer low temperature from the low temperature substances in the storage chamber of the thermal-insulation container to an enclosed space in the mobile refrigerator.

Abstract: Novel methods are provided for the treatment or prevention of B cell mediated conditions in a mammal that comprise administering to said mammal a therapeutically effective amount of a pharmaceutical composition comprising at least one DR6 agonist or DR6 antagonist.

Abstract: A system and method for conversion of a XML document to a HTML document such that the HTML document is traced back to the original XML document. A recipient views the converted XML document as a HTML document and then makes changes to the HTML document. The changes made by the recipient are incorporated into the HTML document as it is traced, i.e., converted, back into the original XML document.