Abstract: A logic gate circuit of TTL, ECL or other configuration, having an output stage including at least one transistor and a control transistor which switches the output stage to either a low or high conductive state in accordance with an input logic control signal supplied to the control transistor. In order to limit the transient change in potential of the internal voltage supply lines of the logic circuit relative to the external voltage supply to which they are connected, which occurs during logic state transitions, the base-emitter path of the output transistor is shunted by the collector-emitter path of a current bypass transistor the base of which is driven by the control transistor. The output transistor may be a composite equivalent transistor formed by a Darlington-connected pair of transistors, and the bypass transistor may itself be such a composite transistor.

Abstract: A TTL compatible buffer circuit responsive to an input signal and having a controlled ramp output is disclosed and includes a low and a high output voltage driver, each driver being comprised of a Darlington pair of transistors, and each driver being separately controlled by its own control circuit. Each control circuit includes at least a capacitor and resistor which are arranged to control the voltage at the base of the upper transistor of the Darlington pair output voltage driver. In this manner, the voltage at the high voltage driver increases in a substantially linear manner when the input signal goes from low to high, and the voltage at the low voltage driver decreases in a substantially linear manner when the input signal goes from high to low. The turn on time of the drivers is thus relatively long. Each control circuit further includes a transistor which permits the respective output voltage driver to turn off quickly.