Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device (WCD) may communicate, during a time period, with a peripheral device via a wireless connection, the wireless connection using a first channel for communication. The WCD may monitor a second channel during a concurrency time of the wireless connection, the second channel using a channel availability check (CAC) to obtain resources for communicating, and transmitting an indication to switch to the second channel for communication. In some aspects, the WCD may communicate with low-latency requirements. Numerous other aspects are described.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device (WCD) may communicate, via a wireless link, with an audio device using a first configuration having first values for communication parameters. The WCD may transmit an indication to switch to a second configuration based at least in part on a configuration switch trigger, the configuration switch trigger being based at least in part on one or more of a link quality metric associated with the wireless link or a change of a use state of the WCD, and the second configuration having second values for the communication parameters associated with a reduction in voltage-induced interference in an audio output of the audio device. Numerous other aspects are described.

Abstract: Aspects relate to transmission control. In some examples, a first apparatus (e.g., a wireless communication device) may output a first packet for transmission to a second apparatus. Subsequently, the first apparatus may suspend a second packet from being output for transmission to the second apparatus. In some examples, the suspension of the second packet may be based on a first voltage level of a power source being less than or equal to a first threshold (e.g., due to the transmission of the first packet).

Abstract: Techniques and apparatus for determining intrinsic resistance and/or battery life of a coin cell battery based on the recovery time of the battery voltage after a significant current draw event. Once the intrinsic resistance and/or battery life is known, a device powered by the coin cell battery can take action to lengthen the battery's useful lifetime. One example technique of operating a device powered by a battery generally includes performing an operation with a relatively high current draw from the battery compared to other operations of the device, determining a recovery time of a voltage of the battery after the operation, and estimating a position of the battery in a lifetime of the battery based on the recovery time.

Abstract: A receiver signal is sampled at a sampling rate equivalent to a chip rate at which chips of a known signal are timed. The resulting receiver signal samples are segmented into receiver signal segments, which are filtered by respective matched filters that are matched to known signal segments segmented from the known signal. Indexes are assigned to elements of the resulting filter response sequences to define an array thereof. Frequency transforms are computed of elements of the filter response sequences in respective columns of the array. Indexes are assigned to elements of the resulting frequency response sequences to define another array thereof. Channel effects imparted on a radio signal are jointly estimated from characteristics of the other array at which at least one local maximum is located.

Abstract: Methods, systems, and devices for wireless communications are described that enable a keep-alive mode for wakeup radio (WUR) operation. A device may determine whether or not at least one keep-alive frame was received at a WUR during an expected on duration of a duty cycle period associated with the WUR. Another device may generate at least one keep-alive frame. The device may output the at least one keep-alive frame for transmission to a WUR of a second wireless node during an expected on duration of a duty cycle period associated with the WUR of the second wireless node.

Abstract: A receiver signal is sampled at a sampling rate equivalent to a chip rate at which chips of a known signal are timed. The resulting receiver signal samples are segmented into receiver signal segments, which are filtered by respective matched filters that are matched to known signal segments segmented from the known signal. Indexes are assigned to elements of the resulting filter response sequences to define an array thereof. Frequency transforms are computed of elements of the filter response sequences in respective columns of the array. Indexes are assigned to elements of the resulting frequency response sequences to define another array thereof. Channel effects imparted on a radio signal are jointly estimated from characteristics of the other array at which at least one local maximum is located.

Abstract: A bifurcated stent-graft and stent-graft delivery system for placement and delivery into an anatomical structure of the body, such as the superior vena cava, are disclosed. The stent-graft includes a first, second and third wire portions that provide strength, flexibility, and resilience. The wire portions are incorporated and joined by a graft fabric that forms a flexible joint that provides increased flexibility. The stent-graft can also include an aperture to allow for unobstructed blood flow from branched or tributary blood vessels such as the azygos vein.

Abstract: Methods and apparatuses are described in which dynamic voltage and frequency scaling may be used to save power when processing packets in a wireless communications device. In some cases, inframe detection may allow the device to determine whether to transition from a first (e.g., lower) voltage level to a second (e.g., higher) voltage level to process one or more packets of a received frame. For some packet types the first voltage level may be maintained. In other cases, the device may determine a bandwidth to use from among multiple bandwidths supported by the device. The bandwidth may be determined based on channel conditions. A voltage level may be identified that corresponds to the determined bandwidth and a processing voltage may be scaled to the identified voltage level. The device may be configured to operate in wireless local area network (WLAN) and/or in a cellular network (e.g., LTE).

Abstract: Methods and apparatuses are described in which dynamic voltage and frequency scaling may be used to save power when processing packets in a wireless communications device. In some cases, inframe detection may allow the device to determine whether to transition from a first (e.g., lower) voltage level to a second (e.g., higher) voltage level to process one or more packets of a received frame. For some packet types the first voltage level may be maintained. In other cases, the device may determine a bandwidth to use from among multiple bandwidths supported by the device. The bandwidth may be determined based on channel conditions. A voltage level may be identified that corresponds to the determined bandwidth and a processing voltage may be scaled to the identified voltage level. The device may be configured to operate in wireless local area network (WLAN) and/or in a cellular network (e.g., LTE).

Abstract: A retractable mobile device power module comprises of a plug to power outlet, a retractable power cord, an adapter, and a retractor. With this design, power supply for mobile devices can be compact and low profile. Besides providing power, this design can be used for data transmission as well.

Abstract: A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.

Abstract: An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.