Abstract: Systems, apparatuses, and methods for implementing a family of lossy sparse load single instruction, multiple data (SIMD) instructions are disclosed. A lossy sparse load unit (LSLU) loads a plurality of values from one or more input vector operands and determines how many non-zero values are included in one or more input vector operands of a given instruction. If the one or more input vector operands have less than a threshold number of non-zero values, then the LSLU causes an instruction for processing the one or more input vector operands to be skipped. In this case, the processing of the instruction of the one or more input vector operands is deemed to be redundant. If the one or more input vector operands have greater than or equal to the threshold number of non-zero values, then the LSLU causes an instruction for processing the input vector operand(s) to be executed.

Abstract: A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.

Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.

Abstract: A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.

Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.

Abstract: Systems, apparatuses, and methods for implementing a family of lossy sparse load single instruction, multiple data (SIMD) instructions are disclosed. A lossy sparse load unit (LSLU) loads a plurality of values from one or more input vector operands and determines how many non-zero values are included in one or more input vector operands of a given instruction. If the one or more input vector operands have less than a threshold number of non-zero values, then the LSLU causes an instruction for processing the one or more input vector operands to be skipped. In this case, the processing of the instruction of the one or more input vector operands is deemed to be redundant. If the one or more input vector operands have greater than or equal to the threshold number of non-zero values, then the LSLU causes an instruction for processing the input vector operand(s) to be executed.

Abstract: Methods of measuring a sample characteristic and accessories for infrared (IR) spectrometers are provided. An accessory includes an input port and an output port having an optical path therebetween, a surface plasmon resonance (SPR) structure for contacting a sample, a mirror system, and an optical element for producing collimated light. The SPR structure produces internally reflected light responsive to broadband IR light, modified by a SPR between the SPR structure and the sample. The mirror system directs the broadband IR light from the input port to the SPR structure and directs the internally reflected light from the SPR structure to the output port, producing output light indicative of a characteristic of the sample associated with the SPR. The optical element is disposed along the optical path between the input port and the output port.

Abstract: Methods of measuring a sample characteristic and accessories for infrared (IR) spectrometers are provided. An accessory includes an input port and an output port having an optical path therebetween, a surface plasmon resonance (SPR) structure for contacting a sample, a mirror system, and an optical element for producing collimated light. The SPR structure produces internally reflected light responsive to broadband IR light, modified by a SPR between the SPR structure and the sample. The mirror system directs the broadband IR light from the input port to the SPR structure and directs the internally reflected light from the SPR structure to the output port, producing output light indicative of a characteristic of the sample associated with the SPR. The optical element is disposed along the optical path between the input port and the output port.

Abstract: The present invention relates to codon-optimized xylanase coding sequences and the expression of xylanases in microbes and yeast. The invention further relates to using multiple copies of the xylanase expression construct for high levels of protein expression. The invention also relates to the use of xylanases as feed or food additives. The invention also relates to methods of expression of enzymes to increase thermotolerance by expressing them in organisms that glycosylate proteins compared to expression that the same enzyme without the glycosylation. Further, the invention relates to methods of preparing feed, enzyme feed additives, and methods of reducing the feed conversion ration or increasing weight gain of animals.

Abstract: The present invention relates to codon-optimized xylanase coding sequences and the expression of xylanases in microbes and yeast. The invention further relates to using multiple copies of the xylanase expression construct for high levels of protein expression. The invention also relates to the use of xylanases as feed or food additives. The invention also relates to methods of expression of enzymes to increase thermotolerance by expressing them in organisms that glycosylate proteins compared to expression that the same enzyme without the glycosylation. Further, the invention relates to methods of preparing feed, enzyme feed additives, and methods of reducing the feed conversion ration or increasing weight gain of animals.

Abstract: The present invention relates to codon-optimized xylanase coding sequences and the expression of xylanases in microbes and yeast. The invention further relates to using multiple copies of the xylanase expression construct for high levels of protein expression. The invention also relates to the use of xylanases as feed or food additives. The invention also relates to methods of expression of enzymes to increase thermotolerance by expressing them in organisms that glycosylate proteins compared to expression that the same enzyme without the glycosylation. Further, the invention relates to methods of preparing feed, enzyme feed additives, and methods of reducing the feed conversion ration or increasing weight gain of animals.