Abstract: A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

Abstract: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.

Abstract: An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.

Abstract: An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.