Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Abstract: A credit-based flow control checking scheme is presented for controlling data communications in a closed loop system comprising a sender, a receiver and a link coupling the sender and receiver. The credit-based scheme includes automatically periodically transmitting a credit query from the receiver to the sender and upon return receipt of a credit acknowledge containing the available credit count maintained by the sender, determining whether credit gain or credit loss has occurred subsequent to initialization of the closed loop system. Along with automatically determining whether credit gain or credit loss has occurred, a method/system is presented for automatically correcting the loss or gain without requiring resetting of the closed loop system.

Abstract: A quiesced and synchronous distributed data processing system includes a primary node, a secondary node and a switch between the primary and secondary nodes. The TOD for the primary node is set depending on the system. The invention sets the TOD for the switch based on the TOD of the primary node. The primary node then verifies the switch TOD. If verified, the TOD for the secondary node is set, based on the TOD of the primary node. Finally, the secondary node self-verifies its TOD.

Abstract: A self-timed link between two elements in a computer system is initialized. Each element sends an initialization request to the other. If successfully received, the elements exchange signals with oscillation-free segments over multiple clock cycles. If successful, the elements indicate to each other that initialization is complete. Optionally, a link operation parameter can be sent with the initialization complete indication for post-initialization link control.

Abstract: An error message is generated by a hardware element of a distributed computer system, when an error is detected. The error message is then forwarded from the hardware element to one or more designated processing nodes of the distributed computer system. The hardware element includes, for instance, a switch element or a communications adapter adapted to report detected errors.

Abstract: A quiesced and synchronous distributed data processing system includes a primary node, a secondary node and a switch between the primary and secondary nodes. The TOD for the primary node is set depending on the system. The invention sets the TOD for the switch based on the TOD of the primary node. The primary node then verifies the switch TOD. If verified, the TOD for the secondary node is set, based on the TOD of the primary node. Finally, the secondary node self-verifies its TOD.

Abstract: An error message is generated by a hardware element of a distributed computer system, when an error is detected. The error message is then forwarded from the hardware element to one or more designated processing nodes of the distributed computer system. The hardware element includes, for instance, a switch element or a communications adapter adapted to report detected errors.

Abstract: A self-timed link between two elements in a computer system is initialized. Each element sends an initialization request to the other. If successfully received, the elements exchange signals with oscillation-free segments over multiple clock cycles. If successful, the elements indicate to each other that initialization is complete. Optionally, a link operation parameter can be sent with the initialization complete indication for post-initialization link control.

Abstract: A credit-based flow control checking scheme is presented for controlling data communications in a closed loop system comprising a sender, a receiver and a link coupling the sender and receiver. The credit-based scheme includes automatically periodically transmitting a credit query from the receiver to the sender and upon return receipt of a credit acknowledge containing the available credit count maintained by the sender, determining whether credit gain or credit loss has occurred subsequent to initialization of the closed loop system. Along with automatically determining whether credit gain or credit loss has occurred, a method/system is presented for automatically correcting the loss or gain without requiring resetting of the closed loop system.

Abstract: A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.