Abstract: Apparatus for synchronizing an internally generated signal with an externally generated periodic or aperiodic signal to generate a periodic output signal phase synchronized with the externally generated signal comprising a local reference signal source, a sampling phase detector, a wide angle phase shifter, and a reference locked phase locked oscillator to achieve the phase alignment of the desired output signal to the input reference signal. The apparatus may contain an optional signal conditioner to condition the input reference signal for processing within the apparatus.

Abstract: A state clock provides a bilevel signal of frequency which is an even multiple of the frequency of an incoming digital signal. A plurality of latches are responsive to the state signal. The outputs of the latches go to corresponding inputs of a memory array, the outputs of which are a plurality of terminals equal in number to the binary bits of a word stored in each address of the memory array. One of the output leads of the memory array passes through one of the state latches and to the output circuit. The other outputs go to the state latches where they are stored temporarily. The state latches are set on the rising transition of the state clock, while an input signal latch is set on the falling transition of the state clock.

Abstract: A frequency tracking, adjustable duty cycle ratio pulse generator that accepts an incoming stream of equally time spaced spike pulses, which go to a first input of an OR gate. The output of the OR gate is fed back to a comparator which has a reference voltage on one input terminal, and receives the feedback voltage from the output of the OR gate through a first switch and through a capacitor. There is a shunt circuit around the capacitor that includes a series resistor and a second switch. The output of the capacitor also connects to a second resistor, to ground. In operation, the first switch is closed when the output of the OR gate is high and when the first switch is closed, the second switch is open, and vice versa. The duty cycle ratio is dependent upon the rate of charge of the capacitor, which is controlled by the capacitance and the second resistor.