Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract: A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a current comparator circuit associated with a DAC element. The apparatus receives an output of a current comparator module, determines calibration data using a finite state machine (FSM) based on the output of the current comparator module, and reduces an offset current at an input of the current comparator module based on the calibration data from the FSM.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.

Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.

Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.