Patents by Inventor Derwin Jallice

Derwin Jallice has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory array on more than one die
    Patent number: 8059441
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: November 15, 2011
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • MEMORY ARRAY ON MORE THAN ONE DIE
    Publication number: 20100149849
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Application
    Filed: February 22, 2010
    Publication date: June 17, 2010
    Inventors: Mohammed Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • Memory array on more than one die
    Patent number: 7692946
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • MEMORY ARRAY ON MORE THAN ONE DIE
    Publication number: 20090001601
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Jeffrey P. Rupley, II, Edward A. Brekelbaum, Gabriel H. Loh, Bryan Black
  • Method and apparatus for hardening a static random access memory cell from single event upsets
    Patent number: 6285580
    Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: September 4, 2001
    Assignees: BAE Systems Information, Electronic Systems Integration, Inc.
    Inventors: Ho Gia Phan, Derwin Jallice, Bin Li, Joseph Hoffman
  • Single event upset (SEU) hardened static random access memory cell
    Patent number: 6208554
    Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The first and second sets of isolation transistors are coupled to the first and second set of cross-coupled transistors, respectively, such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: March 27, 2001
    Assignee: Lockheed Martin Corporation
    Inventors: Ho Gia Phan, Derwin Jallice, Bin Li, Joseph Hoffman