Abstract: An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.

Abstract: An extended segmented precharge architecture for static random access memories includes a logic circuitry on an SRAM chip to keep track as to whether a given bit line has been read out. As long as a given bit line has not been read out, precharge of the equalization lines is eliminated thereby increasing access cycle time and reducing power dissipation. The architecture can be applied to any size SRAM of any organization.

Abstract: A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to select mode, there appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such a false transition as an actual transition, local clock pulse generators are used which only detect high to low transitions in the chip select mode.

Abstract: A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.

Abstract: A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors are reverse biased or clamped to zero to prevent any leakage paths.

Abstract: A fused, redundancy selection circuit is disclosed which is disabled by the absence of a chip select signal. The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristic. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off.