Abstract: A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: Methods of depositing material onto substrate comprising: depositing a first seed material onto a wafer substrate, the wafer substrate having a face that defines a normal to the substrate, wherein the first seed material is deposited at a pressure of 10 to 20 mTorr to form a pre-seed layer on the wafer substrate, wherein the pre-seed layer has a surface roughness from 1 to 10 nm; depositing a second seed material onto at least a portion of the pre-seed layer at an off-normal incidence angle to form a seed layer on at least a portion of the pre-seed layer; and depositing a bulk piezoelectric material onto at least a portion of the seed layer to form a bulk piezoelectric layer having a c-axis tilt of 35 degrees or greater and a surface roughness of 4.5 nm or less. Structures and bulk acoustic wave resonators containing same are also included.

Abstract: Methods for depositing bulk layer crystalline material having a predetermined c-axis tilt on a substrate include a first step of depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and a second step of depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: A deposition system is disclosed that allows for growth of inclined c-axis piezoelectric material structures. The system integrates various sputtering modules to yield high quality films and is designed to optimize throughput lending it to a high-volume in manufacturing environment. The system includes two or more process modules including an off-axis module constructed to deposit material at an inclined c-axis and a longitudinal module constructed to deposit material at normal incidence; a central wafer transfer unit including a load lock, a vacuum chamber, and a robot disposed within the vacuum chamber and constructed to transfer a wafer substrate between the central wafer transfer unit and the two or more process modules; and a control unit operatively connected to the robot.

Abstract: A method for manufacturing an acoustic device includes providing a substrate, providing a bottom electrode over the substrate, providing a sacrificial layer on the bottom electrode, patterning the bottom electrode and the sacrificial layer, polishing the sacrificial layer such that a portion of the sacrificial layer remains on the bottom electrode, and removing the remaining portion of the sacrificial layer via a cleaning process such that a surface roughness of the bottom electrode is maintained. By performing the polishing such that a portion of the sacrificial layer remains on the bottom electrode and subsequently removing that portion of the sacrificial layer via a cleaning process that maintains the surface roughness of the bottom electrode, the subsequent growth of a piezoelectric layer on the bottom electrode can be substantially improved.

Abstract: A fluidic device and a method of preventing isolation material from bleed-out therein is described herein. The fluidic device includes a bulk acoustic wave resonator structure defining at least one surface area region on which a functionalization material is disposed and the resonator structure includes a repelling area. The fluidic device also includes isolation material disposed on the resonator structure and away from the at least one surface area region. The repelling area is configured to prevent the isolation material from extending into the at least one surface area region. Further, an electronic board may be operably attached to the resonator structure and the isolation material may be disposed in a gap therebetween to electrically isolate electrical contacts and form a fluidic channel.

Abstract: A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: Bulk acoustic wave resonator structures include a bulk layer with inclined c-axis hexagonal crystal structure piezoelectric material supported by a substrate. The bulk layer may be prepared without first depositing a seed layer on the substrate. The bulk material layer has a c-axis tilt of about 32 degrees or greater. The bulk material layer may exhibit a ratio of shear coupling to longitudinal coupling of 1.25 or greater during excitation. A method for preparing a crystalline bulk layer having a c-axis tilt includes depositing a bulk material layer directly onto a substrate at an off-normal incidence. The deposition conditions may include a pressure of less than 5 mTorr and a deposition angle of about 35 degrees to about 85 degrees.

Abstract: A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: Bulk acoustic wave resonator structures include a bulk layer with inclined c-axis hexagonal crystal structure piezoelectric material supported by a substrate. The bulk layer may be prepared without first depositing a seed layer on the substrate. The bulk material layer has a c-axis tilt of about 32 degrees or greater. The bulk material layer may exhibit a ratio of shear coupling to longitudinal coupling of 1.25 or greater during excitation. A method for preparing a crystalline bulk layer having a c-axis tilt includes depositing a bulk material layer directly onto a substrate at an off-normal incidence. The deposition conditions may include a pressure of less than 5 mTorr and a deposition angle of about 35 degrees to about 85 degrees.

Abstract: A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: Bulk acoustic wave resonator structures include a bulk layer with inclined c-axis hexagonal crystal structure piezoelectric material supported by a substrate. The bulk layer may be prepared without first depositing a seed layer on the substrate. The bulk material layer has a c-axis tilt of about 32 degrees or greater. The bulk material layer may exhibit a ratio of shear coupling to longitudinal coupling of 1.25 or greater during excitation. A method for preparing a crystalline bulk layer having a c-axis tilt includes depositing a bulk material layer directly onto a substrate at an off-normal incidence. The deposition conditions may include a pressure of less than 5 mTorr and a deposition angle of about 35 degrees to about 85 degrees.

Abstract: Methods for depositing bulk layer crystalline material having a predetermined c-axis tilt on a substrate include a first step of depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and a second step of depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.

Abstract: One aspect of the disclosure relates to a contact within a dielectric layer to a source/drain terminal of a field-effect-transistor (FET). The contact may include: a titanium-tantalum-silicide at a surface of the source/drain terminal; a barrier layer over the titanium-tantalum-silicide; and a metal over the barrier layer and extending to a top surface of the dielectric layer.

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.