Patents by Inventor Deshan ZHANG

Deshan ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250225091
    Abstract: The present disclosure provides a method for PCIE data transmission. The method includes: determining whether the length of a PCIE data packet to be transmitted is less than a preset length; when it is determined that the length of the PCIE data packet is less than the preset length, performing data transmission on the PCIE data packet by means of a space of a base address register and a protocol converter; and when it is determined that the length of the PCIE data packet is greater than or equal to the preset length, performing data reading/writing on the PCIE data packet in a DMA manner. Therefore, the utilization rate of a PCIE bandwidth is improved, and the running reliability of a host is improved.
    Type: Application
    Filed: May 22, 2023
    Publication date: July 10, 2025
    Applicant: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang WANG, Shengcai LU, Qi MOU, Wei LIU, Deshan ZHANG
  • Patent number: 12277079
    Abstract: Provided is a direct memory access architecture, including: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component; the control register is configured to obtain descriptor address information; the read descriptor storage component is configured to store a read descriptor obtained by using the control register; the write descriptor storage component is configured to store a write descriptor obtained by using the control register; the read command transfer component is configured to send, to the read data moving component, a read command; the write command transfer component is configured to send, to the write data moving component, a write command.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 15, 2025
    Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang Wang, Qi Mu, Deshan Zhang, Wei Liu, Rengang Li
  • Publication number: 20240419617
    Abstract: Provided is a direct memory access architecture, including: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component; the control register is configured to obtain descriptor address information; the read descriptor storage component is configured to store a read descriptor obtained by using the control register; the write descriptor storage component is configured to store a write descriptor obtained by using the control register; the read command transfer component is configured to send, to the read data moving component, a read command; the write command transfer component is configured to send, to the write data moving component, a write command.
    Type: Application
    Filed: November 28, 2022
    Publication date: December 19, 2024
    Applicant: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang WANG, Qi MU, Deshan ZHANG, Wei LIU, Rengang LI
  • Patent number: 12079556
    Abstract: Provided is a synchronous FIFO, including a data storage circuit, a first logic circuit, a second logic circuit and indication circuits. The data storage circuit includes N first registers, N first multiplexers and N first deciders, where N is a positive integer; and the N first registers and the N first multiplexers are alternately connected. Based on the registers, the synchronous FIFO builds a storage required by the FIFO, and primarily includes the registers, the multiplexers and the deciders, the use of an RAM is avoided, that is, there is no need to occupy the RAM, and there is no need to perform RAM read-write enabling and address control, thereby avoiding wasting RAM resources. In designs with lower storage depth requirements, few resources are occupied, so that a chip area is greatly reduced, the cost is reduced, and layout and wiring are more convenient.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: September 3, 2024
    Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang Wang, Deshan Zhang, Qi Mou
  • Publication number: 20240256748
    Abstract: Provided is a synchronous FIFO, including a data storage circuit, a first logic circuit, a second logic circuit and indication circuits. The data storage circuit includes N first registers, N first multiplexers and N first deciders, where N is a positive integer; and the N first registers and the N first multiplexers are alternately connected. Based on the registers, the synchronous FIFO builds a storage required by the FIFO, and primarily includes the registers, the multiplexers and the deciders, the use of an RAM is avoided, that is, there is no need to occupy the RAM, and there is no need to perform RAM read-write enabling and address control, thereby avoiding wasting RAM resources. In designs with lower storage depth requirements, few resources are occupied, so that a chip area is greatly reduced, the cost is reduced, and layout and wiring are more convenient.
    Type: Application
    Filed: June 22, 2022
    Publication date: August 1, 2024
    Applicant: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang WANG, Deshan ZHANG, Qi MOU
  • Patent number: 11659173
    Abstract: Disclosed is a method and chip for vertically filtering an image, including: caching and reading image data; calling a filter to vertically filter the image data to obtain first filtered data; updating the image data according to the first filtered data, and judging whether a to-be-read row is the last row of the image data; if not, updating the to-be-read row to the next row of the to-be-read row, and returning to execute the step of caching the image data; and if so, determining the vertically filtered image data. In the present application, point-by-point feedback is changed to row-by-row feedback according to an algorithm principle of a digital recursive filter and the characteristics of an image chip.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 23, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang Wang, Deshan Zhang, Qi Mou
  • Publication number: 20220417508
    Abstract: Disclosed is a method and chip for vertically filtering an image, including: caching and reading image data; calling a filter to vertically filter the image data to obtain first filtered data; updating the image data according to the first filtered data, and judging whether a to-be-read row is the last row of the image data; if not, updating the to-be-read row to the next row of the to-be-read row, and returning to execute the step of caching the image data; and if so, determining the vertically filtered image data. In the present application, point-by-point feedback is changed to row-by-row feedback according to an algorithm principle of a digital recursive filter and the characteristics of an image chip.
    Type: Application
    Filed: November 5, 2020
    Publication date: December 29, 2022
    Inventors: Hongliang WANG, Deshan ZHANG, Qi MOU
  • Patent number: 11431578
    Abstract: Provided are a method, apparatus, device for determining a network anomaly behavior. The method includes: acquiring network data traffic in a target network, and determining each data packet contained in the network data traffic as a node of a complete graph, to construct a data complete graph; optimizing the data complete graph into a minimum spanning tree by a Kruskal algorithm, and determining each node of the minimum spanning tree as a cluster center; classifying all data packets contained in the network data traffic based on cluster centers, to acquire data element sets corresponding to the cluster centers respectively; and determining an anomaly behavior in the target network based on a type of each of the data element sets, wherein the type of the data element set is determined by a type of a network attack contained in the network data traffic.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 30, 2022
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Dongdong Su, Wei Liu, Deshan Zhang
  • Publication number: 20210344569
    Abstract: Provided are a method, apparatus, device for determining a network anomaly behavior. The method includes: acquiring network data traffic in a target network, and determining each data packet contained in the network data traffic as a node of a complete graph, to construct a data complete graph; optimizing the data complete graph into a minimum spanning tree by a Kruskal algorithm, and determining each node of the minimum spanning tree as a cluster center; classifying all data packets contained in the network data traffic based on cluster centers, to acquire data element sets corresponding to the cluster centers respectively; and determining an anomaly behavior in the target network based on a type of each of the data element sets, wherein the type of the data element set is determined by a type of a network attack contained in the network data traffic.
    Type: Application
    Filed: August 30, 2019
    Publication date: November 4, 2021
    Applicant: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Dongdong SU, Wei LIU, Deshan ZHANG