Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array; a first electrode, the first electrode including a first portion located in the display area and a second portion located in the peripheral area; an electrode connection line, the electrode connection line is located in the peripheral area, the electrode connection line is electrically connected to the second portion; a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first portion.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and a data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array; a first electrode, the first electrode including a first portion located in the display area and a second portion located in the peripheral area; an electrode connection line, the electrode connection line is located in the peripheral area, the electrode connection line is electrically connected to the second portion; a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first portion.

Abstract: A liquid crystal display panel and a display device. The liquid crystal display panel includes a display region and an opening region in the display region; the display region includes a plurality of sub-pixels, the display region includes a first edge and a second edge opposite to the first edge, the display region includes a first region between the opening region and the first edge and a second region between the opening region and the second edge, an orthographic projection of the opening region on the first edge respectively coincides with orthographic projections of the first region and the second region on the first edge, the plurality of sub-pixels comprise a main sub-pixel in the first region and a secondary sub-pixel in the second region, and an area of the main sub-pixel is smaller than an area of the secondary sub-pixel.

Abstract: A liquid crystal display panel and a display device. The liquid crystal display panel includes a display region and an opening region in the display region; the display region includes a plurality of sub-pixels, the display region includes a first edge and a second edge opposite to the first edge, the display region includes a first region between the opening region and the first edge and a second region between the opening region and the second edge, an orthographic projection of the opening region on the first edge respectively coincides with orthographic projections of the first region and the second region on the first edge, the plurality of sub-pixels comprise a main sub-pixel in the first region and a secondary sub-pixel in the second region, and an area of the main sub-pixel is smaller than an area of the secondary sub-pixel.

Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.

Abstract: The present disclosure provides an in cell touch screen including a plurality of touch electrodes and a shade structure, wherein the shade structure includes a plurality of first shade bars arranged in parallel along a first direction and a plurality of second shade bars arranged in parallel along a second direction perpendicular to the first direction; and the first shade bars are conductive, and the touch electrodes are electrically connected to the first shade bars, respectively.

Abstract: The present disclosure provides an in cell touch screen including a plurality of touch electrodes and a shade structure, wherein the shade structure includes a plurality of first shade bars arranged in parallel along a first direction and a plurality of second shade bars arranged in parallel along a second direction perpendicular to the first direction; and the first shade bars are conductive, and the touch electrodes are electrically connected to the first shade bars, respectively.

Abstract: A mask, comprising an opaque region, a first semi-transparent region, and a second semi-transparent region. The transmittance of the second semi-transparent region is less than that of the first semi-transparent region. The mask solves the over-etching problem caused by the difference between the thicknesses of photoresist in different regions.

Abstract: The present disclosure relates to the field of photolithography technologies. Disclosed is a mask comprising a transparent substrate, the transparent substrate being provided thereon with a semi-transmitting film layer and a light barrier layer to form a non-transmitting region, a semi-transmitting region, and a full transmitting region, the transparent substrate being further provided with a light extinction film layer located at a vicinity of the full transmitting region to weaken an intensity of ultraviolet light transmitting through the vicinity of the full transmitting region. The size of the via formed after an exposure process with the mask is less affected by a change in the thickness of the photoresist surrounding the via.