Patents by Inventor Desikan Iyadurai

Desikan Iyadurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Translation lookaside buffer prediction mechanism
    Patent number: 7987337
    Abstract: A memory management unit includes a translation lookaside buffer including a page table. The page table includes M entries where M is an integer greater than zero. A register interface selects one of the M entries. The translation lookaside buffer calculates an effective address based on the selected one of the M entries while at least one of mapping the selected one of the M entries to an index and selecting a set of the M entries based on a control signal.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 26, 2011
    Assignee: Marvell International Ltd.
    Inventors: Michael W. Morrow, Dennis M. O'Connor, Desikan Iyadurai
  • Translation lookaside buffer prediction mechanism
    Patent number: 7434027
    Abstract: According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: October 7, 2008
    Assignee: Marvell International Ltd.
    Inventors: Michael W. Morrow, Dennis M. O'Connor, Desikan Iyadurai
  • Translation lookaside buffer prediction mechanism
    Publication number: 20070022270
    Abstract: According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.
    Type: Application
    Filed: September 27, 2006
    Publication date: January 25, 2007
    Inventors: Michael Morrow, Dennis O'Connor, Desikan Iyadurai
  • Translation lookaside buffer prediction mechanism
    Patent number: 7162609
    Abstract: According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: January 9, 2007
    Assignee: Marvell International Ltd.
    Inventors: Michael W. Morrow, Dennis M. O'Connor, Desikan Iyadurai
  • Digital coaxial cable LAN
    Publication number: 20060218593
    Abstract: The invention relates to a coaxial cable local area network (LAN) for digitally communicating client generated data between clients of the cable LAN. The cable LAN has adapters in communication with both the clients and other adapters of the cable LAN. Connected through coaxial cable, these adapters generate and communicate data transmitting signals that take advantage of the operating frequency spectrum of the coaxial cable so as to not interfere with the operating frequency of the client data within the coaxial cable. Other features are disclosed.
    Type: Application
    Filed: January 3, 2006
    Publication date: September 28, 2006
    Inventors: Amir Afshary, Desikan Iyadurai, Brian Mears, Gregory Tucker
  • Translation lookaside buffer prediction mechanism
    Publication number: 20050125628
    Abstract: According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.
    Type: Application
    Filed: December 3, 2003
    Publication date: June 9, 2005
    Inventors: Michael Morrow, Dennis O'Connor, Desikan Iyadurai