Patents by Inventor Desmond W. Young

Desmond W. Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5619651
    Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
    Type: Grant
    Filed: August 4, 1995
    Date of Patent: April 8, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Desmond W. Young
  • Patent number: 5619652
    Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: April 8, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Mark A. Travaglio, Desmond W. Young
  • Patent number: 5600799
    Abstract: An interface system for transferring information between a local area-network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system, An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
    Type: Grant
    Filed: October 5, 1995
    Date of Patent: February 4, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Desmond W. Young, James R. Hamstra
  • Patent number: 5524250
    Abstract: A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: June 4, 1996
    Assignee: Silicon Graphics, Inc.
    Inventors: Greg Chesson, In-whan Choi, Yuh-wen Lin, Jeannine M. Smith, Daniel Yau, Desmond W. Young
  • Patent number: 5513320
    Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: April 30, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Desmond W. Young, James R. Hamstra
  • Patent number: 5511166
    Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
    Type: Grant
    Filed: August 8, 1995
    Date of Patent: April 23, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Mark A. Travaglio, Desmond W. Young, James R. Hamstra, David C. Brief
  • Patent number: 5487152
    Abstract: An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: January 23, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Desmond W. Young
  • Patent number: 5423008
    Abstract: A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification desired. As addresses and access-type signals appear on the bus, the comparator simultaneously compares the bus information to access event register information to determine if the bus access meets access event register criteria. When matches occur, the comparator emits an appropriate signal to an event masking component. The local processor also loads the event masking component to selectively mask off unwanted event notifications as well as those performed by itself.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: June 6, 1995
    Assignee: Silicon Graphics, Inc.
    Inventors: Desmond W. Young, Kianoosh Naghshineh, William D. Schwaderer