Abstract: An analogue multiplier circuit has an input coefficient voltage dependent adjustment of its frequency response. The multiplier contains a multiplier cell (MC) with an RF input (Vin+, Vin?) and a coefficient signal input (Vcoeff+, Vcoeff?), one or more capacitors (Cp1, Cp2) as peaking capacitors, which one contact connects to the multiplier cell (MC) and the other to a variable resistance (Mp1, Mp2), i.e. a MOS transistor, and a control circuit (CT) for controlling the variable resistance (Mp1, Mp2). The control circuit (CT) is connected to the coefficient signal input (Vcoeff+, Vcoeff?) of the multiplier. In the case of a four-quadrant multiplier a rectifier (RT) is connected between the coefficient input (Vcoeff+, Vcoeff?) of the multiplier and the control circuit (CT).

Abstract: A circuit arrangement for an LVDS driver, which uses combined bipolar and MOSFET technology with at least two MOSFETs, is shown, wherein a multiplier circuit is connected to an output stage of the LVDS driver and the multiplier circuit is controlled by means of an automatic control circuit, which generates control signals for controlling a current source of the multiplier circuit and for controlling the amplification factor of differential input signals of the multiplier circuit. Advantages of the invention are that it enables said technology, in which semi-conductor components are used in bipolar techniques (e.g. NPN and/or PNP transistors) (as well as MOS technology), to take advantage of the high speed of the bipolar elements compared with MOS elements.