Abstract: The invention relates to a phase comparison circuit for determining the phase deviation between an input signal and a reference signal. The input signal is integrated during two consecutive defined integration intervals which are derived from the reference signal. The integral values assigned to the integration intervals are weighted and the difference is formed. The output signal of the phase comparison circuit is derived from the result of forming this difference.

Abstract: A circuit arrangement for a television receiver including a video text decoder (30), producing signals from the video text data from which control signals for a picture display device can be derived. The circuit arrangement further including a television signal decoder (1), deriving from the television signal via a low-pass filter arrangement (15) the luminance signal which can be taken from the luminance signal output (18). The low-pass filter arrangement (15) has a first attenuation characteristic for suppressing the chrominance signal and a second attenuation characteristic for allowing all video text data to pass. The second attenuation characteristic of the low-pass filter arrangement (15) is used during the period of time in which the video text data occur. The input of the video text decoder (30) is coupled to the luminance signal output (18) of the television signal decoder (1).

Abstract: An input signal comprising pulses in periodical intervals and being present as a series of digital sampling values is applied to a correlator for generating a correlator output signal which assumes an extreme value in the case of a pulse. The correlator comprises a chain of at least two cascaded delay members, the first of which receives the input signal. A pulse and pulse-free interval, respectively is associated with each delay member of the series, the delay members succeeding each other in the same manner as the pulses or pulse-free intervals occur. All but at most one delay member at the beginning or end of the chain can store just all sampling values of the associated pulse or pulse-free interval. The input signal of the first delay member and the output signals of all delay members are applied to a combination circuit which linearly combines and integrates the signals and forms the output signal of the correlator.

Abstract: The invention relates to a circuit arrangement for increasing the resolution of color contours. A slope detector detects the slope of the luminance signal and, when a predetermined slope value is exceeded, produces a detection signal for energizing a counter. The counter controls an edge enhancement circuit for a color difference signal, in which, as soon as the counter is energizing, the value of the color difference signal is stored and is available as an output signal. After a predetermined number of equidistant clock pulses has been counted, the edge enhancement circuit (7, 16) supplies the actual color difference signal value. If before the end of the counting operation, a new detection signal is produced, then the edge enhancement circuit briefly receives and stores the actual color difference signal value, and the counter starts a new counting cycle.

Abstract: In a circuit arrangement for synchronization of the phase of a frequency-divided signal with an edge of finite slope of an essentially periodic synchronizing signal with an oscillator supplying a clock signal, a frequency divider which generates the frequency-divided signal and a phase detector which comprises a first comparator for coarse phase detection, a second comparator for fine phase detection and a selector circuit which derives a resulting phase signal applied to the oscillator to control the frequency of the clock signal and originating from the first comparator in the case of large phase variations and from the second comparator in the case of small phase variations, precise adjustment to the edge is nevertheless achieved in the case of an amplitude-discrete synchronizing signal with limited time resolution because of the fact that the synchronizing signal is applied to the phase detector as a sequence of amplitude-discrete values which is formed by sampling the synchronizing signal with the clock