Abstract: An integral Bi-CMOS logic circuit includes a pair of first transistors and a pair of second transistors. The pair of the first transistors includes a P-type MOS transistor receiving an input signal through its gate, and an NPN-type bipolar transistor with its base connected to the drain of the P-type MOS transistor outputting a first output signal. The pair of the second transistors includes an N-type MOS transistor receiving the input signal through its gate, and a PNP bipolar transistor with its base connected to the drain of the N-type MOS transistor outputting the first output signal. A final output signal is outputted through a common emitter of the bipolar transistors.

Abstract: A semiconductor chip protection circuit has a transmission gate TG.sub.11 disposed between an input pin 11 and an input terminal of an internal circuit 12, and two further transmission gates TG.sub.12, TG.sub.13 respectively connected between the input terminal of the internal circuit and a power terminal V.sub.DD, and between the input terminal and a ground terminal. Two additional transmission gates TG.sub.14, TG.sub.15 are connected respectively between an output terminal of the internal circuit and the power terminal, and between the output terminal and ground. At least one final transmission gate TG.sub.16 is connected between the power terminal and ground. Electrostatic charges are smoothly discharged because of the low resistance value of the N-type and P-type transistors of gates TG.sub.11 to TG.sub.16.