Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device which includes the steps of preparing an active matrix provided with a transistor, diffusion regions, an isolation region, a bit line, a first insulating layer and a second insulating layer; forming a first conductive layer and then a dielectric layer on the active matrix; carrying out a rapid thermal annealing (RTA) for producing nuclei in the dielectric layer; forming a second conductive on top of the dielectric layer; carrying out a thermal annealing in a furnace; forming a capacitor structure provided with a top electrode, a capacitor thin film and a bottom electrode by patterning the second conductive, the dielectric and the first conductive layers into a first predetermined configuration; carrying out a first recovery; forming a third insulating layer on the capacitor structure and the second insulating layer; patterning the third insulating layer to form a first opening and a second opening; and carrying out a second recover

Abstract: A method for manufacturing a ferroelectric memory device including the steps of forming a polysilicon plug to connect a transistor through an interlayer dielectric (ILD) layer which is formed on a semiconductor substrate incorporating the transistor therein, forming a first conductive layer on the polysilicon plug and the ILD layer, forming a ferroelectric layer on the first conductive layer, carrying out a heat treatment for crystallization of the ferroelectric layer in a presence of an inert gas, forming a second conductive layer on the ferroelectric layer, and patterning the second conductive layer, the ferroelectric layer and the first conductive layer to form a ferroelectric capacitor.

Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device which includes the steps of preparing an active matrix provided with a transistor, diffusion regions, an isolation region, a bit line, a first insulating layer and a second insulating layer; forming a first conductive layer and then a dielectric layer on the active matrix; carrying out a rapid thermal annealing (RTA) for producing nuclei in the dielectric layer; forming a second conductive on top of the dielectric layer; carrying out a thermal annealing in a furnace; forming a capacitor structure provided with a top electrode, a capacitor thin film and a bottom electrode by patterning the second conductive, the dielectric and the first conductive layers into a first predetermined configuration; carrying out a first recovery; forming a third insulating layer on the capacitor structure and the second insulating layer; patterning the third insulating layer to form a first opening and a second opening; and carrying out a second recover

Abstract: A plasma display panel comprising a transparent substrate having a first part, a second part and a third part, said second part located between said first part and said third part, a first electrode formed on the first part, a first dielectric layer formed on an entire surface of the transparent substrate with the first electrode, a fluorescent material coated on the first dielectric layer located over the second part, a second electrode vertically spaced from the first dielectric layer and having a prominence toward the first dielectric layer positioned on the third part, the second dielectric layer orthogonal to the first electrode, a third electrode formed on the second electrode positioned on the first electrode, a second dielectric layer vertically spaced from the first dielectric layer and formed under the second electrode including the prominence, the second dielectric layer contacted with the first dielectric layer formed in the third part, and a third dielectric layer formed on the second electrode i

Abstract: A plasma display panel for preventing a discharging operation in a non-displaying area and thus progressing the contrast ratio according to the present invention is disclosed. The plasma display panel comprises a first substrate and a second substrate which are provided with each of inner faces opposite to each other. Between the first and second substrates, barrier ribs arranged toward a first direction are separated parallel to each other with a space. On the inner face of the first substrate, first electrodes are arranged parallel with each other toward a second direction which is orthogonal with the first direction. In addition, dot type second electrodes, which are connected with a pair of first electrodes and are exposed to a space between the pair of first electrodes, are arranged on the inner face of the first substrate. Between the barrier ribs on the inner face of the second substrate, there are placed third electrodes which are arranged parallel with the first direction.

Abstract: A plasma display panel is disclosed including a transparent insulating substrate having a plurality of striped grooves, whose portions between the grooves serve as barrier ribs; vertical transparent electrodes each of which is formed in each groove; a fluorescent layer formed on the vertical transparent electrode; horizontal electrodes in strip arrangement having a predetermined distance between one another, and being perpendicular to the transparent vertical electrodes; and supporting means which are respectively located on the edge portions of the substrate for supporting the horizontal electrodes.

Abstract: A plasma display panel is disclosed including: a transparent insulating substrate; a plurality of transparent electrodes in a strip arrangement with each electrode having a groove that runs along the median of its surface and has a predetermined width and depth at its center, and side walls on both sides of the groove, the side walls serving as barrier ribs; a fluorescent layer formed in each groove; and a plurality of electrodes in strip arrangement having a predetermined distance between one another and perpendicular to the transparent electrodes, the electrodes being supported by supporting means formed on a predetermined portion of barrier rib located on the edge portion of the substrate.