Abstract: An array substrate includes first and second lines on a substrate and formed of a metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode connected to the data line; a drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing the gate insulating layer and the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening and contacting the drain electrode.

Abstract: An array substrate includes first and second lines on a substrate and formed of a metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode connected to the data line; a drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing the gate insulating layer and the drain electrode; and a pixel electrode positioned on the gate insulating layer and in the opening and contacting the drain electrode.

Abstract: An array substrate for a liquid crystal display device includes first and second lines on a substrate and spaced apart from each other, the first and second lines formed of a first metallic material; a gate electrode connected to the first line; a gate insulating layer on the first and second lines and the gate electrode and including a groove, the groove exposing the substrate and positioned between the first and second lines; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; a data line crossing the first and second lines and on the gate insulating layer; a source electrode on the semiconductor layer and connected to the data line; a drain electrode on the semiconductor layer and spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode and including an opening, the opening exposing a portion of the gate insulating layer and an end of the drain electrode; and a pixel electrode positioned on the gate in

Abstract: A motion-vector operation device includes an upper memory composed of first and second banks that store motion vectors of a lower block group belonging to a macroblock, a left memory storing motion vectors of a right block group belonging to a macroblock, and an estimator predicting a motion vector of a current block with reference to the motion vectors stored in the first and second banks of the upper memory and the left memory in accordance with an operation mode and a position of the current block in a super macroblock.

Abstract: Example embodiments are directed to an apparatus and method for enhancing an image. The method may include extracting contrast data from color image data, generating low resolution image data and band pass image data from the contrast data using a Laplacian pyramid, generating global brightness enhanced image data from the low resolution image data to enhance an overall brightness, generating local contrast ratio enhanced image data from the band pass image data to enhance a local contrast, and/or generating enhanced contrast data from the global brightness enhanced image data and the local contrast ratio enhanced data. The apparatus may include circuitry for performing similar operations.

Abstract: A motion-vector operation device includes an upper memory composed of first and second banks that store motion vectors of a lower block group belonging to a macroblock, a left memory storing motion vectors of a right block group belonging to a macroblock, and an estimator predicting a motion vector of a current block with reference to the motion vectors stored in the first and second banks of the upper memory and the left memory in accordance with an operation mode and a position of the current block in a super macroblock.

Abstract: A deblocking filter includes a current macroblock buffer memory configured to store video data of a current macroblock to be filtered, a side macroblock buffer memory configured to store a portion of video data of neighboring macroblocks located on the side of the current macroblock, a register buffer array configured to store video data read from the current macroblock buffer memory for current filtering, video data read from the side macroblock buffer memory, and data of neighboring macroblocks, and an edge filter that is connected to the register buffer array and is configured to perform horizontal or vertical filtering on an edge of a subblock of the current macroblock of video data and to perform the other of horizontal or vertical filtering on an edge of a subsequent subblock of the current macroblock of the video data, simultaneously. Vertical filtering uses the data from the neighboring macroblocks and horizontal filtering uses the video data from the side macroblock buffer memory.

Abstract: An interface device according to the present invention interfaces with a host by an m-bit unit. A flag signal generator circuit generates a mode flag signal indicating whether a data transfer mode of the interface device is a multi-transfer mode. A control circuit operates responsive to information indicating whether an address from the host is a data width aligned address and whether the address thus transmitted belongs to a data width aligned address range. The control circuit causes m-bit data from the host to be continuously stored in a first-in first-out memory. Data continuously stored in the memory is at once transmitted to a high-speed bus connected to the interface device.

Abstract: An interface device according to the present invention interfaces with a host by an m-bit unit. A flag signal generator circuit generates a mode flag signal indicating whether a data transfer mode of the interface device is a multi-transfer mode. A control circuit operates responsive to information indicating whether an address from the host is a data width aligned address and whether the address thus transmitted belongs to a data width aligned address range. The control circuit causes m-bit data from the host to be continuously stored in a first-in first-out memory. Data continuously stored in the memory is at once transmitted to a high-speed bus connected to the interface device.