Abstract: The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

Abstract: A memory system includes a memory device having a plurality of memory blocks and a subcommand storage circuit, and a memory controller for controlling the memory device, wherein the memory device is capable of being in one or more of a ready state, a first busy state, and a second busy state, and wherein the subcommand is stored in the subcommand storage circuit when the subcommand is received from the memory controller in the first busy state and the subcommand is executable after the first busy state is released, and the subcommand stored in the subcommand storage circuit is executed after the memory device is changed to the ready state.

Abstract: A memory system includes a memory device having a plurality of memory blocks and a subcommand storage circuit, and a memory controller for controlling the memory device, wherein the memory device is capable of being in one or more of a ready state, a first busy state, and a second busy state, and wherein the subcommand is stored in the subcommand storage circuit when the subcommand is received from the memory controller in the first busy state and the subcommand is executable after the first busy state is released, and the subcommand stored in the subcommand storage circuit is executed after the memory device is changed to the ready state.

Abstract: A data storage apparatus includes a controller configured to control data input to and output from a storage according to a request transmitted from a host apparatus, a buffer memory configured to store data transmitted and received between the host apparatus and the storage, and the storage including a plurality of memory cells and a verification component configured to verify a state of a target memory cell before write data is programmed in the target memory cell while the write data is transmitted from the host apparatus in response to a write request of the host apparatus.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a controller configured to generate and output a first command for a program operation in response to a request from a host, and generate and output a second command for a read scan operation when the memory system is powered on after an abnormal power-off is detected; and a semiconductor memory device configured to perform the program operation on a page basis in response to the first command, perform the read scan operation in response to the second command, and perform a single read operation per page using a set read voltage during the read scan operation.

Abstract: There are provided a memory system and a method for operating the same. A memory system includes: a semiconductor memory device for outputting a ready/busy (R/B) signal by performing an internal operation in response to an operation command, and outputting status data by performing a status check operation in response to a status check command; and a controller for outputting the operation command and the status check command to the semiconductor memory device, and determining validity of the status data, based on the R/B signal.

Abstract: A semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a controller configured to generate and output a first command for a program operation in response to a request from a host, and generate and output a second command for a read scan operation when the memory system is powered on after an abnormal power-off is detected; and a semiconductor memory device configured to perform the program operation on a page basis in response to the first command, perform the read scan operation in response to the second command, and perform a single read operation per page using a set read voltage during the read scan operation.

Abstract: A semiconductor memory device includes a status storage unit and a status check unit. The status storage unit stores first status data indicating an operation status of the memory cell array. The status check unit generates second status data, based on the first status data and an operation of the memory cell array.

Abstract: There are provided a memory system and a method for operating the same. A memory system includes: a semiconductor memory device for outputting a ready/busy (R/B) signal by performing an internal operation in response to an operation command, and outputting status data by performing a status check operation in response to a status check command; and a controller for outputting the operation command and the status check command to the semiconductor memory device, and determining validity of the status data, based on the R/B signal.

Abstract: Provided herein may be a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, control logic, a status storage unit, and an operating characteristic checking unit. The memory cell array may include memory cells. The peripheral circuit may perform an operation for writing data to the memory cell array, reading data from the memory cell array, or erasing data written to the memory cell array. The control logic may control the peripheral circuit so that a data write operation, a data read operation or a data erase operation is performed. The status storage unit may store an operational status of the memory cell array as a first status value. The operating characteristic checking unit may receive an operating characteristic value, and generate a second status value via a comparison with an operation threshold value.

Abstract: Provided herein may be a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, control logic, a status storage unit, and an operating characteristic checking unit. The memory cell array may include memory cells. The peripheral circuit may perform an operation for writing data to the memory cell array, reading data from the memory cell array, or erasing data written to the memory cell array. The control logic may control the peripheral circuit so that a data write operation, a data read operation or a data erase operation is performed. The status storage unit may store an operational status of the memory cell array as a first status value. The operating characteristic checking unit may receive an operating characteristic value, and generate a second status value via a comparison with an operation threshold value.

Abstract: Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.

Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

Abstract: A method of operating a semiconductor device includes performing a program operation on selected memory cells of a selected page, and selectively performing a soft erase operation on memory cells having threshold voltages greater than a reference voltage, among the selected memory cells, to reduce a width of a threshold voltage distribution of the selected memory cells.

Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

Abstract: A method of operating a semiconductor device includes performing a program operation on selected memory cells of a selected page, and selectively performing a soft erase operation on memory cells having threshold voltages greater than a reference voltage, among the selected memory cells, to reduce a width of a threshold voltage distribution of the selected memory cells.

Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

Abstract: A non-volatile memory device includes: a semiconductor pillar stretched perpendicularly to a substrate; a plurality of memory cells stacked along the semiconductor pillar; a bit line coupled with a first end of the semiconductor pillar; a first source line coupled with one of the first end and a second end of the semiconductor pillar; a second source line disposed over the bit line and the first source line; a first switch having a first end coupled with the first source line and a second end coupled with a first voltage supplier, and controlling whether to supply a first voltage to the first source line; and a second switch having a first end coupled with the first source line and a second end coupled with the second source line, and controlling whether or not to supply a second voltage supplied from the second source line to the first source line.