Abstract: A power MOSFET that includes deep source field electrodes, the power MOSFET including one trench that includes an insulated gate and another trench that does not include an insulated gate, both trenches including a source field electrode, a source region adjacent the one trench and no source region adjacent the another trench, and a high conductivity contact region between the two trenches and disposed to divert at least a portion of the avalanche current away from regions under the source region and toward the high conductivity contact region.

Abstract: A power semiconductor device that includes a trench power MOSFET with deep source field electrodes and an integrated Schottky diode.

Abstract: Semiconductor power devices with improved electrical characteristics are disclosed including rectifying contacts on a specially prepared semiconductor surface with little or no additional exposure to other chemical treatments, with oxide passivation and edge termination at a face of the semiconductor substrate adjacent to and surrounding the power device. The edge termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize a portion of the substrate face and preferably self-aligned to the device. The passivated, edge-terminated devices exhibit improved characteristics relative to passivated devices with characteristics approaching those of the native semiconductor with the additional advantages of passivation protection. Methods for making and using the devices are also disclosed.

Abstract: A silicon carbide lateral metal-oxide-semiconductor field-effect transistor (SiC LMOSFET) having a self-aligned drift region and method for forming the same is provided. Specifically, the SiC LMOSFET includes a source region, a drift region and a drain region. The source and drain regions are implanted using non self-aligned technology (i.e., prior to formation of the gate electrode and the gate oxide layer), while the drift region is implanted using self-aligned technology (i.e., after formation of the gate electrode and the gate oxide layer). By self-aligning the drift region to the gate electrode, the overlap between the two is minimized, which reduces the capacitance of the device. When capacitance is reduced, performance is improved.

Abstract: A silicon carbide lateral metal-oxide-semiconductor field-effect transistor (SiC LMOSFET) having a self-aligned drift region and method for forming the same is provided. Specifically, the SiC LMOSFET includes a source region, a drift region and a drain region. The source and drain regions are implanted using non self-aligned technology (i.e., prior to formation of the gate electrode and the gate oxide layer), while the drift region is implanted using self-aligned technology (i.e., after formation of the gate electrode and the gate oxide layer). By self-aligning the drift region to the gate electrode, the overlap between the two is minimized, which reduces the capacitance of the device. When capacitance is reduced, performance is improved.

Abstract: A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) includes a layer of silicon carbide semiconductor material having a p-type conductivity, source and drain regions having n-type conductivities disposed in the silicon carbide semiconductor layer, and an insulated gate electrode disposed on the silicon carbide semiconductor layer. A silicon carbide semiconductor substrate having an n-type conductivity, supports the silicon carbide semiconductor layer. A second layer of silicon carbide semiconductor material having a p-type conductivity, is disposed between the substrate and the first silicon carbide semiconductor layer to prevent parasitic transistor effects. A sinker region having an n-type conductivity extends from the source contact to the silicon carbide semiconductor substrate to ground the substrate.

Abstract: A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

Abstract: A method for forming a contact window in a semiconductor device is provided. Specifically, the present invention provides a method for removing a passivation layer over a pad metal without using a photo mask. The method generally comprises applying a photo resist layer over a passivation layer, which itself is positioned over a substrate and a pad metal. A portion of the photo resist layer is then developed using ultraviolet light. The developed portion is etched away with a developer to reveal the passivation layer over the pad metal, which is subsequently removed to yield a contact window.

Abstract: A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: The invention provides a method for the production of high quality thermally grown oxide on top of silicon carbide. The high quality oxide is obtained by selectively removing the carbon from the silicon carbide in the areas where oxide formation is desired or required.

Abstract: Semiconductor power devices with improved electrical characteristics are disclosed including rectifying contacts on a specially prepared semiconductor surface with little or no additional exposure to other chemical treatments, with oxide passivation and edge termination at a face of the semiconductor substrate adjacent to and surrounding the power device. The edge termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize a portion of the substrate face and preferably self-aligned to the device. The passivated, edge-terminated devices exhibit improved characteristics relative to passivated devices with characteristics approaching those of the native semiconductor with the additional advantages of passivation protection. Methods for making and using the devices are also disclosed.

Abstract: The invention provides a method for the production of high quality thermally grown oxide on top of silicon carbide. The high quality oxide is obtained by selectively removing the carbon from the silicon carbide in the areas where oxide formation is desired or required.

Abstract: Semiconductor power devices with improved electrical characteristics are disclosed including rectifying contacts on a specially prepared semiconductor surface with little or no additional exposure to other chemical treatments, with oxide passivation and edge termination at a face of the semiconductor substrate adjacent to and surrounding the power device. The edge termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize a portion of the substrate face and preferably self-aligned to the device. The passivated, edge-terminated devices exhibit improved characteristics relative to passivated devices with characteristics approaching those of the native semiconductor with the additional advantages of passivation protection. Methods for making and using the devices are also disclosed.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A silicon carbide LMOSFET having a self-aligned gate with gate reach-through protection and method for making same. The LMOSFET includes a first layer of SiC semiconductor material having a p-type conductivity and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. An etched trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material thereby forming a gate structure. A channel region is defined in the first layer beneath the gate structure. The gate structure is rounded or buried to provide a current path in the channel region which avoids sharp corners.

Abstract: A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, includes a first layer of SiC semiconductor material having a p-type conductivity, and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. The n-type conductivities of the source and drain regions are greater than the n-type conductivity of the second SiC layer. A trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material. The layers of oxide and metallic material form a gate structure.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A method of forming a laterally-varying charge profile in a silicon carbide substrate includes the steps of forming a silicon nitride layer on a polysilicon layer formed on the silicon carbide substrate, and patterning the silicon nitride layer to provide a plurality of silicon nitrite layer segments which are spaced apart in the lateral direction and which are provided with openings therebetween which are of varying widths. The polysilicon layer is oxidized using the layer segments as an oxidation mask to form a silicon dioxide layer of varying thickness from the polysilicon layer and to form a polysilicon layer portion therebeneath of varying thickness. The silicon dioxide layer and silicon nitride layer segments are removed, and a dopant is ion implanted into the silicon carbide substrate using the polysilicon layer portion of varying thickness as an implantation mask to form a laterally-varying charge profile in the silicon carbide substrate.

Abstract: A lateral silicon carbide (SiC) semiconductor device includes a SIC substrate of a first conductivity type, a SiC epitaxial layer of the first conductivity type on the substrate and a SiC surface layer on the SiC epitaxial layer. The SiC surface layer has a SiC first region of the first conductivity type, a SiC lateral drift region of a second conductivity type opposite to that of the first conductivity type adjacent the first region and forming a p-n junction therewith, and a SiC second region of the second conductivity type spaced apart from the first region by the drift region. By providing the drift region with a variable doping level which increases in a direction from the first region to the second region, compact SiC semiconductor devices such as high-voltage diodes or MOSFETs can be formed which can operate at high voltages, high temperatures and high frequencies, thus providing a substantial advantage over known devices.