Patents by Inventor Deva N. Pattanaya

Deva N. Pattanaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4868620
    Abstract: An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.
    Type: Grant
    Filed: July 14, 1988
    Date of Patent: September 19, 1989
    Assignee: Pacific Bell
    Inventors: James E. Kohl, Eric J. Wildi, Robert S. Scott, Deva N. Pattanaya, Michael S. Adler