Patents by Inventor Deva N. Pattanayak
Deva N. Pattanayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10546750Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: GrantFiled: January 5, 2016Date of Patent: January 28, 2020Assignee: Vishay-SiliconixInventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
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Patent number: 10229988Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.Type: GrantFiled: December 11, 2017Date of Patent: March 12, 2019Assignee: Vishay-SiliconixInventors: Naveen Tipirneni, Deva N. Pattanayak
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Publication number: 20180114852Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.Type: ApplicationFiled: December 11, 2017Publication date: April 26, 2018Inventors: Naveen Tipirneni, Deva N. Pattanayak
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Patent number: 9853140Abstract: An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring.Type: GrantFiled: December 31, 2012Date of Patent: December 26, 2017Assignee: Vishay-SiliconixInventors: Naveen Tipirneni, Deva N. Pattanayak
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Patent number: 9842911Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.Type: GrantFiled: May 30, 2012Date of Patent: December 12, 2017Assignee: Vishay-SiliconixInventors: Naveen Tipirneni, Deva N. Pattanayak
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Patent number: 9431249Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.Type: GrantFiled: December 1, 2011Date of Patent: August 30, 2016Assignee: Vishay-SiliconixInventor: Deva N. Pattanayak
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Publication number: 20160225622Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: ApplicationFiled: January 5, 2016Publication date: August 4, 2016Applicant: Vishay-SiliconixInventors: Hamilton LU, The-Tu CHAU, Kyle TERRILL, Deva N. PATTANAYAK, Sharon SHI, Kuo-In CHEN, Robert XU
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Patent number: 9230810Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: GrantFiled: August 31, 2010Date of Patent: January 5, 2016Assignee: Vishay-SiliconixInventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
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Patent number: 8883580Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: GrantFiled: December 27, 2012Date of Patent: November 11, 2014Assignee: Vishay-SiliconixInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
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Publication number: 20140235023Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: ApplicationFiled: December 27, 2012Publication date: August 21, 2014Applicant: VISHAY-SILICONIXInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-in Chen
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Publication number: 20140183624Abstract: An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: VISHAY-SILICONIXInventors: Naveen Tipirneni, Deva N. Pattanayak
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Publication number: 20130320462Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: VISHAY-SILICONIXInventors: Naveen Tipirneni, Deva N. Pattanayak
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Publication number: 20130140633Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: VISHAY-SILICONIXInventor: Deva N. Pattanayak
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Patent number: 8368126Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.Type: GrantFiled: April 7, 2008Date of Patent: February 5, 2013Assignee: Vishay-SiliconixInventors: Deva N. Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo-In Chen
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Publication number: 20110095359Abstract: A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.Type: ApplicationFiled: June 25, 2010Publication date: April 28, 2011Applicant: VISHAY-SILICONIXInventors: Naveen Tipirneni, Deva N. Pattanayak
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Publication number: 20110049682Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: VISHAY-SILICONIXInventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu
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Patent number: 7833863Abstract: Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.Type: GrantFiled: April 22, 2008Date of Patent: November 16, 2010Assignee: Vishay-SiliconixInventors: Deva N Pattanayak, Robert Xu
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Patent number: 7704836Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: GrantFiled: March 31, 2008Date of Patent: April 27, 2010Assignee: Siliconix incorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
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Publication number: 20100019316Abstract: A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: ApplicationFiled: September 29, 2009Publication date: January 28, 2010Applicant: Siliconix incorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
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Patent number: 7557409Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: GrantFiled: January 26, 2007Date of Patent: July 7, 2009Assignee: Siliconix IncorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi