Patents by Inventor Devadatta Bhat

Devadatta Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711241
    Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: July 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ashutosh Anand, Shankarnarayan Bhat, Nikhil Sudhakaran, Praveen Raghuraman, Nishi Bhushan Singh, Anand Bhat, Abhinav Kothiala, Sanjay Muchini, Arun Balachandar, Devadatta Bhat
  • Publication number: 20160293272
    Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Ashutosh Anand, Shankarnarayan Bhat, Nikhil Sudhakaran, Praveen Raghuraman, Nishi Bhushan Singh, Anand Bhat, Abhinav Kothiala, Sanjay Muchini, Arun Balachandar, Devadatta Bhat
  • Publication number: 20160077151
    Abstract: A method and apparatus for testing secure blocks is provided. The method begins when instructions for testing a secure memory are loaded using a parallel testing interface. Instructions for testing the non-secure memory may be resident on the device as Built-In-Self-Test (BIST) instructions. In that case, the instructions are then accessed through the standard test access. Testing occurs simultaneously for the secure memory and the non-secure memory using both the parallel interface and the standard test interface. Testing both the secure memory blocks and the non-secure memory blocks using the parallel and standard test interfaces saves time during the test process.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Ashutosh Anand, Shankarnarayan Bhat, Arun Balachandar, Nikhil Sudhakaran, Praveen Raghuraman, Devadatta Bhat, Sanjay Muchini