Abstract: A non-transitory computer readable storage medium storing instructions executable by one or more processors of a distributed computer system to perform operations including determining whether a power consumed by the distributed computer system is greater than a power allocated to the distributed computer system, responsive to determining the power consumed by the distributed computer system is greater than the power allocated to the distributed computer system, determining whether all jobs being processed by the distributed computer system are processing at a lowest power state for each job, wherein a job includes one or more calculations performed by the one or more processors of the distributed computer system and responsive to determining all jobs being processed by the distributed computer system are processing at a lowest power state for each job, suspending a job having a lowest priority among all jobs being processed by the distributed computer system is shown.

Abstract: Some embodiments of the invention may operate to measure a first output performance metric value associated with a current operation frequency of a processor, to set a trial operation frequency of the processor, and to measure a second output performance metric value associated with the trial operation frequency. If the measured performance variation is less than a specified acceptable performance variation, the trial operation frequency may be selected as a subsequent determined operation frequency.

Abstract: Some embodiments of the invention may operate to measure a first output performance metric value associated with a current operation frequency of a processor, to set a trial operation frequency of the processor, and to measure a second output performance metric value associated with the trial operation frequency. If the measured performance variation is less than a specified acceptable performance variation, the trial operation frequency may be selected as a subsequent determined operation frequency.

Abstract: Systems and methods of managing threads provide for selecting a thread for execution and identifying a target performance state of a processor core based on the thread. Identifying the target performance state may include applying a priority of the thread to a mapping policy to obtain the target performance state. In one embodiment, a transition of the selected core to the target performance state can be initiated and the thread can be scheduled for execution by the processor core.

Abstract: Systems and methods of managing processor threads provide for selecting a thread for execution by a processing architecture having a plurality of cores. A target core is selected from the plurality of cores based on a thread power value that corresponds to the thread. The thread is scheduled for execution by the target core.

Abstract: Systems and methods of managing software threads provide for selecting a software thread for execution by a processing architecture having a plurality of processing cores and a cooling module. A target core is selected from the plurality of cores based on the effectiveness of the cooling module with regard to each of the plurality of cores, and the selected thread is scheduled for execution by the target core.

Abstract: Systems and methods of managing workloads provide for detecting a workload for a system having a first processor core with a first performance indicator and a second processor core with a second performance indicator. The workload is scheduled based on the first and second performance indicators settings. In one embodiment, a performance feasibility index is calculated for each core based on the core's frequency setting and utilization and the workload is assigned to the core associated with the highest index.

Abstract: A method is described that, in order to change an operational state of a resource within a computing system that is shared by components of the computing system so that the computing system's power consumption is altered, sends a packet over one or more nodal hops within a packet based network within the computing system. The packet contains information pertaining to the power consumption alteration.

Abstract: Systems and methods of managing processing system performance provide for determining a utilization of a processing system over a time quantum. A trend in the utilization of the processing system is also determined, where the trend can be used to select a performance state for the processing system. In one embodiment, the processing system includes a central processing unit (CPU).

Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

Abstract: Methods and apparatuses for coordination of power state management in and electronic system.

Abstract: Provided is a technique for power and performance management of one or more storage devices. With a power and performance management agent, a power change notification identifying a power set point is received and a power state of at least one storage device is adjusted.

Abstract: A current level of power consumption of a system is monitored by a power consumption controller. When the current level of power consumption exceeds power guidelines, the power consumption controller adjusts the power consumption of one or more components in the system at a time by at least one power consumption level. Adjusting such power consumption level may have an impact on the performance of the system. Various techniques may be used to reduce (ramp down) power consumption or allow increase (ramp up) in power consumption. A power management policy may use one or combination of such techniques in order to enable the system to deliver the high performance while still maintaining the power consumption of the system within the power guidelines.

Abstract: A processor that includes a digital throttle to monitor the activity of the execution pipeline and to change a frequency of a first or second PLL clock within a single clock cycle based on a power state.