Patents by Inventor Devadatta V. Bodas

Devadatta V. Bodas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7315952
    Abstract: Methods and apparatuses for coordination of power state management in and electronic system.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: January 1, 2008
    Assignee: Intel Corporation
    Inventors: Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan, David Poisner, Lance E. Hacking
  • Patent number: 7272741
    Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan, David Poisner, Bernard J. Lint, Lance E. Hacking
  • Patent number: 7210048
    Abstract: Power consumption by a computer system may vary all the time based upon software and the workload. Facility such as data centers host multiple of computer systems. With continuous growing demand for power and cooling of computer systems, data centers face limitations on their ability to provide the power and cooling capability. These limitations are occasionally exasperated by problems in either power or cooling systems. The computer systems may have a method to maintain total power consumption below a set target level. An enterprise power and thermal manager, EPTM, may change this setting dynamically to improve efficiency of supporting power and cooling infrastructure. In addition, the EPTM may use this ability to improve performance, availability and to provide ability to implement various administrative policies.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventor: Devadatta V. Bodas
  • Patent number: 7174471
    Abstract: Provided is a technique for power and performance management of one or more storage devices. With a power and performance management agent, a power change notification identifying a power set point is received and a power state of at least one storage device is adjusted.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: February 6, 2007
    Assignee: Intel Corporation
    Inventors: Eshwari P. Komarla, Vincent J. Zimmer, Devadatta V. Bodas
  • Patent number: 7124309
    Abstract: A processor that includes a digital throttle to monitor the activity of the execution pipeline and to change a frequency of a first or second PLL clock within a single clock cycle based on a power state.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: James S. Burns, Devadatta V. Bodas, Stefan I Rusu, Sudhir Muthyalapati
  • Patent number: 6925573
    Abstract: Power consumption in a system is monitored by a controller. The controller uses a power consumption policy to determine when the power consumption of the system needs to be adjusted. Adjustment is made by gradually reducing power consumptions of one or more components in the system or allowing the one or more components to gradually increase the power consumption.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventor: Devadatta V. Bodas
  • Patent number: 6804616
    Abstract: A method is described for computing the power consumption of a device. The method comprises (1) determining the number and type of each of a plurality of components comprising a system, (2) determining a component power consumption for each of the plurality of components, and (3) determining a device power consumption by summing the component power consumptions of all of the plurality of components. A rack holds multiple systems, provides power to the systems and cool air to remove thermal energy from the systems. Power and cooling requirements for a rack are determined by (1) determining the number and type of components comprising each of the plurality of systems, (2) determining component power consumption for each of the plurality of components, (3) determining a system power consumption for each system by summing the component power consumptions of all components in each system, and (4) determining a rack power consumption by summing the system power consumptions for all systems.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: October 12, 2004
    Assignee: Intel Corporation
    Inventor: Devadatta V. Bodas
  • Patent number: 6795781
    Abstract: A method and apparatus for a compiler, or similar computer language translating device, to translate a computer language into a sequence of electronic instructions to be executed at run-time by at least one functional unit in a computer. At compile time, the compiler creates and analyzes the sequential order of the electronic instructions to determine exact moments when the functional unit will begin to, or complete, executing the electronic instructions. Consequently, the compiler can predict time intervals when the functional unit will be in use, or idling between instructions. In addition, the compiler knows the delay time, or latency, involved in powering up and powering down the functional unit. The compiler compares the use times, or idle times, to the latency, and creates power-controlling instructions to be embedded into the sequence of electronic instructions. The power-controlling instructions are to control power to the functional units at run-time.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventors: Tomm Aldridge, Devadatta V. Bodas
  • Publication number: 20040163001
    Abstract: Power consumption by a computer system may vary all the time based upon software and the workload. Facility such as data centers host multiple of computer systems. With continuous growing demand for power and cooling of computer systems, data centers face limitations on their ability to provide the power and cooling capability. These limitations are occasionally exasperated by problems in either power or cooling systems. The computer systems may have a method to maintain total power consumption below a set target level. An enterprise power and thermal manager, EPTM, may change this setting dynamically to improve efficiency of supporting power and cooling infrastructure. In addition, the EPTM may use this ability to improve performance, availability and to provide ability to implement various administrative policies.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 19, 2004
    Inventor: Devadatta V. Bodas
  • Patent number: 6686666
    Abstract: Pads are arranged as an integrated circuit (IC) footprint, and are formed in a stackup that includes an insulating layer and multiple signal routing layers. The footprint has a polygonal shape. There is an inner pad region, a middle pad region that surrounds the inner pad region, and an outer pad region that surrounds the middle pad region. Some of the pads of each pad region are connected to a respective group of signal lines. Some of the signals that are connected to pads of the outer region which are located in a corner of the polygonal shape are routed out of the footprint in a different layer than the one used to route signal lines that are connected to pads of the outer region which are located between two adjacent corners of the polygonal shape.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: February 3, 2004
    Assignee: Intel Corporation
    Inventor: Devadatta V. Bodas
  • Publication number: 20040002823
    Abstract: A method and apparatus for a compiler, or similar computer language translating device, to translate a computer language into a sequence of electronic instructions to be executed at run-time by at least one functional unit in a computer. At compile time, the compiler creates and analyzes the sequential order of the electronic instructions to determine exact moments when the functional unit will begin to, or complete, executing the electronic instructions. Consequently, the compiler can predict time intervals when the functional unit will be in use, or idling between instructions. In addition, the compiler knows the delay time, or latency, involved in powering up and powering down the functional unit. The compiler compares the use times, or idle times, to the latency, and creates power-controlling instructions to be embedded into the sequence of electronic instructions. The power-controlling instructions are to control power to the functional units at run-time.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Inventors: Tomm Aldridge, Devadatta V. Bodas
  • Publication number: 20030214030
    Abstract: Pads are arranged as an integrated circuit (IC) footprint, and are formed in a stackup that includes an insulating layer and multiple signal routing layers. The footprint has a polygonal shape. There is an inner pad region, a middle pad region that surrounds the inner pad region, and an outer pad region that surrounds the middle pad region. Some of the pads of each pad region are connected to a respective group of signal lines. Some of the signals that are connected to pads of the outer region which are located in a corner of the polygonal shape are routed out of the footprint in a different layer than the one used to route signal lines that are connected to pads of the outer region which are located between two adjacent corners of the polygonal shape.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 20, 2003
    Inventor: Devadatta V. Bodas
  • Publication number: 20030126475
    Abstract: Power consumption in a system is monitored by a controller. The controller uses a power consumption policy to determine when the power consumption of the system needs to be adjusted. Adjustment is made by gradually reducing power consumptions of one or more components in the system or allowing the one or more components to gradually increase the power consumption.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventor: Devadatta V. Bodas
  • Publication number: 20030115000
    Abstract: A method is described for computing the power consumption of a device. The method comprises (1) determining the number and type of each of a plurality of components comprising a system, (2) determining a component power consumption for each of the plurality of components, and (3) determining a device power consumption by summing the component power consumptions of all of the plurality of components. A rack holds multiple systems, provides power to the systems and cool air to remove thermal energy from the systems. Power and cooling requirements for a rack are determined by (1) determining the number and type of components comprising each of the plurality of systems, (2) determining component power consumption for each of the plurality of components, (3) determining a system power consumption for each system by summing the component power consumptions of all components in each system, and (4) determining a rack power consumption by summing the system power consumptions for all systems.
    Type: Application
    Filed: December 13, 2001
    Publication date: June 19, 2003
    Inventor: Devadatta V. Bodas
  • Publication number: 20030088799
    Abstract: A system is disclosed for the regulation of electrical component temperature and power consumption rate through the reconfiguration between different interconnect bus widths.
    Type: Application
    Filed: November 5, 2001
    Publication date: May 8, 2003
    Inventor: Devadatta V. Bodas