Patents by Inventor Devan Burke
Devan Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200034946Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.Type: ApplicationFiled: August 5, 2019Publication date: January 30, 2020Applicant: Intel CorporationInventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
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Patent number: 10540260Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.Type: GrantFiled: February 23, 2018Date of Patent: January 21, 2020Assignee: INTEL CORPORATIONInventors: Travis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke
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Patent number: 10522113Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.Type: GrantFiled: December 29, 2017Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
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Publication number: 20190378322Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Applicant: Intel CorporationInventors: Devan Burke, Abhishek Venkatesh, Travis Schluessler
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Publication number: 20190355084Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.Type: ApplicationFiled: May 17, 2018Publication date: November 21, 2019Applicant: Intel CorporationInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Publication number: 20190355091Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.Type: ApplicationFiled: May 17, 2018Publication date: November 21, 2019Applicant: Intel CorporationInventors: John Gierach, Abhishek Venkatesh, Travis Schluessler, Devan Burke, Tomer Bar-On, Michael Apodaca
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Patent number: 10445923Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.Type: GrantFiled: September 28, 2017Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Devan Burke, Abhishek Venkatesh, Travis Schluessler
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Patent number: 10417734Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.Type: GrantFiled: September 7, 2017Date of Patent: September 17, 2019Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
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Patent number: 10417731Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.Type: GrantFiled: April 24, 2017Date of Patent: September 17, 2019Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
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Publication number: 20190272612Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.Type: ApplicationFiled: February 6, 2019Publication date: September 5, 2019Inventors: Abhishek R. Appu, Joydeep Ray, Peter L. Doyle, Subramaniam Maiyuran, Devan Burke, Philip R. Laws, ElMoustapha Ould-Ahmed-Vall, Altug Koker
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Publication number: 20190266069Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Applicant: Intel CorporationInventors: Travis Schluessler, Abhishek Venkatesh, Elmoustapha Ould-Ahmed-Vall, John Gierach, Tomer Bar On, Devan Burke
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Publication number: 20190259128Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.Type: ApplicationFiled: January 24, 2019Publication date: August 22, 2019Inventors: Abhishek Venkatesh, Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak, Devan Burke, Travis T. Schluessler
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Publication number: 20190244422Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.Type: ApplicationFiled: February 6, 2019Publication date: August 8, 2019Inventors: Peter L. Doyle, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Philip R. Laws, Altug Koker
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Publication number: 20190244418Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.Type: ApplicationFiled: February 6, 2019Publication date: August 8, 2019Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Devan Burke, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle
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Publication number: 20190205736Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: Amit Bleiweiss, Abhishek Venkatesh, Gokce Keskin, John Gierach, Oguz Elibol, Tomer Bar-On, Huma Abidi, Devan Burke, Jaikrishnan Menon, Eriko Nurvitadhi, Pruthvi Gowda Thorehosur Appajigowda, Travis T. Schluessler, Dhawal Srivastava, Nishant Patel, Anil Thomas
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Publication number: 20190156533Abstract: Embodiments are generally directed to minimum or maximum sample indexing in a control surface. An embodiment of an apparatus includes a graphics processor including: a sampler to sample a value; one or more of a color unit or a depth unit; and at least one minimum or maximum sample (min/max) setter subunit for the color unit or depth unit, the min/max setter subunit to receive a new sample value, store the sample value in a resource containing a plurality of sample values, and update indexing include index values for one or more of a minimum sample value and a maximum sample value in the plurality of sample values of the resource.Type: ApplicationFiled: November 20, 2017Publication date: May 23, 2019Applicant: Intel CorporationInventor: Devan Burke
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Publication number: 20190096117Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: Intel CorporationInventors: Devan Burke, Abhishek Venkatesh, Travis Schluessler
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Patent number: 10242496Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.Type: GrantFiled: April 24, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Peter L. Doyle, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Philip R. Laws, Altug Koker
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Patent number: 10242494Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.Type: GrantFiled: April 1, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Devan Burke, Philip R. Laws, Subramanian Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle
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Patent number: 10235735Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.Type: GrantFiled: April 10, 2017Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Abhishek Venkatesh, Prasoonkumar Surti, Slawomir Grajewski, Louis Feng, Kai Xiao, Tomasz Janczak, Devan Burke, Travis T. Schluessler