Patents by Inventor Devanathan Balasundaram

Devanathan Balasundaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method to improve input output command latency by dynamic size logical to physical caching
    Patent number: 10831656
    Abstract: A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 10, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventors: Jameer Babasaheb Mulani, Anindya Rai, Devanathan Balasundaram
  • Partial reset of memory controller
    Patent number: 10719267
    Abstract: Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 21, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Anindya Rai, Jameer Babasaheb Mulani, Devanathan Balasundaram
  • SYSTEM AND METHOD TO IMPROVE INPUT OUTPUT COMMAND LATENCY BY DYNAMIC SIZE LOGICAL TO PHYSICAL CACHING
    Publication number: 20200117598
    Abstract: A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Jameer Babasaheb MULANI, Anindya RAI, Devanathan BALASUNDARAM
  • PARTIAL RESET OF A MEMORY CONTROLLER
    Publication number: 20190369911
    Abstract: Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Anindya Rai, Jameer Babasaheb Mulani, Devanathan Balasundaram