Patents by Inventor Devanathan Varadarajan

Devanathan Varadarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12033711
    Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 9, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Varun Singh
  • Patent number: 12009045
    Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: June 11, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Varun Singh
  • Publication number: 20240170083
    Abstract: An electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory, and a second data input coupled to a data output of the register; an inverter circuit having a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, where the controller is configured to determine whether the memory has a fault based on the fault input of the controller.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Devanathan Varadarajan
  • Publication number: 20240120016
    Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 11, 2024
    Inventors: Devanathan Varadarajan, Lei Wu
  • Patent number: 11881275
    Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Adolfo Cano, Devanathan Varadarajan, Anthony Martin Hill
  • Publication number: 20230409435
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Application
    Filed: August 30, 2023
    Publication date: December 21, 2023
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Publication number: 20230324456
    Abstract: An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.
    Type: Application
    Filed: July 29, 2022
    Publication date: October 12, 2023
    Inventors: Devanathan Varadarajan, Benjamin Niewenhuis
  • Patent number: 11748202
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: September 5, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Publication number: 20230253062
    Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Devanathan VARADARAJAN, Varun SINGH
  • Publication number: 20230229338
    Abstract: An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.
    Type: Application
    Filed: August 31, 2022
    Publication date: July 20, 2023
    Inventor: Devanathan Varadarajan
  • Publication number: 20230185633
    Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Devanathan VARADARAJAN, Varun SINGH, Jose Luis FLORES, Rejitha NAIR, David Matthew THOMPSON
  • Publication number: 20230146764
    Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 11, 2023
    Inventors: Francisco Adolfo CANO, Devanathan VARADARAJAN, Anthony Martin HILL
  • Patent number: 11631472
    Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 18, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Devanathan Varadarajan, Varun Singh
  • Patent number: 11568951
    Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 31, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Adolfo Cano, Devanathan Varadarajan, Anthony Martin Hill
  • Publication number: 20220413966
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Application
    Filed: September 1, 2022
    Publication date: December 29, 2022
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Publication number: 20220319627
    Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Devanathan VARADARAJAN, Varun SINGH
  • Patent number: 11436090
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 6, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Patent number: 11373726
    Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 28, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Devanathan Varadarajan, Varun Singh
  • Publication number: 20220199188
    Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Inventors: DEVANATHAN VARADARAJAN, VARUN SINGH
  • Publication number: 20220197750
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Inventors: DEVANATHAN VARADARAJAN, RAMAKRISHNAN VENKATASUBRAMANIAN, VARUN SINGH