Abstract: Power semiconductor packages are provided. In one example, the power semiconductor package includes a first semiconductor die, a second semiconductor die, and a submount having a first side and a second side opposing the first side. The first semiconductor die is coupled to the first side of the submount, and the second semiconductor die is coupled to the second side of the submount.

Abstract: Power semiconductor device packages and methods for manufacturing the same are provided. In one example, a power semiconductor device package may include a housing, a submount, and a semiconductor die on the submount. The power semiconductor device package may further include a bond structure. In one example, the bond structure may be at least partially exposed through a side of the housing and may be configured to provide a heat dissipation path through the side of the housing. In one example, the bond structure may be planarized relative to a side of the housing such that at least a portion of the bond structure is co-planar with the side of the housing.

Abstract: Power semiconductor device packages and methods for manufacturing the same are provided. In one example, a power semiconductor device package may include a housing, a submount, and a conjoined semiconductor die structure on the submount. The conjoined semiconductor die structure may include at least two semiconductor die having a common substrate. The conjoined semiconductor die structure may be cut from a semiconductor wafer and may be packaged based on die viability data indicative of an operability of each respective semiconductor die of the at least two semiconductor die.

Abstract: Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

Abstract: A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

Abstract: A power package includes an assembly having a first power package side, a second power package side, a third power package side, and a fourth power package side; first power terminals arranged at the first power package side; second power terminals arranged at the second power package side; first signal terminals arranged at the third power package side; second signal terminals arranged at the fourth power package side. The power package in addition includes where a location of the first power terminals at the first power package side is symmetrical with respect to a location of the second power terminals at the second power package side and/or a location of the first signal terminals on third power package side is symmetrical with respect to a location of the second signal terminals on fourth power package side.

Abstract: Example aspects of the present disclosure are directed to power semiconductor device packages and methods of forming the same. In one example, a power semiconductor device package includes a submount, a semiconductor die on the submount, a die-attach material coupling the semiconductor die to the submount, and a housing formed around at least a portion of the submount and the semiconductor die. The semiconductor die includes a semiconductor structure, a metallization structure on a major surface of the semiconductor structure, and one or more support structures on the metallization structure. In one example, the die-attach material is provided around the one or more support structures between the semiconductor die and the submount.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate.

Abstract: Semiconductor device packages are provided. In one example, a semiconductor device package comprises a first structure having a first surface in the semiconductor device package, a second structure having a second surface in the semiconductor device package, and an adhesion promoting layer in contact with the first surface on a first side and the second surface on a second side. The adhesion promoting layer comprises a polyimide containing repeating units derived from a tetracarboxylic dianhydride and at least one diamine containing a functional group.

Abstract: Semiconductor device packages are provided. In one example, the semiconductor device package includes a semiconductor die. The semiconductor die includes a wide bandgap semiconductor material. The semiconductor die includes a metallization layer on a surface of the semiconductor die. The semiconductor device package includes a submount. The metallization of the semiconductor die is directly bonded to the submount.

Abstract: Die-attach materials for semiconductor device packages are provided. In one example, a semiconductor device package includes a submount. The semiconductor device package includes a semiconductor die comprising a wide bandgap semiconductor. The semiconductor device package includes a die-attach layer between the submount and the semiconductor die. The die-attach layer comprises gold (Au), tin (Sn), and cobalt (Co).

Abstract: Semiconductor packages and, more particularly, semiconductor packages with increased power handling capabilities are disclosed. Semiconductor packages may include lead frame structures and corresponding housings that incorporate semiconductor die. To promote increased current and voltage capabilities, exemplary semiconductor packages include one or more arrangements of creepage extension structures, lead frame structures that may include integral thermal pads, additional thermal elements, and combinations thereof. Creepage extension structures may be arranged as part of top sides of semiconductor packages along with thermal pads of lead frame structures and additional thermal elements. Creepage extension structures may also be arranged as part of top sides and along on one or more peripheral edges of semiconductor packages to promote further increases in power handling.

Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.

Abstract: Semiconductor packages are provided. In one example, a semiconductor package includes a submount. The semiconductor package further includes a semiconductor die on the submount. The submount defines a base plane, and the submount includes at least one stud protrusion extending from the base plane in a direction toward the semiconductor die.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: Semiconductor packages are provided. In one example, a semiconductor package includes a submount having a first surface and a second surface opposing the first surface. The semiconductor package includes at least one semiconductor die attached to the second surface of submount. The semiconductor package includes an insulating portion on the second surface of the submount and on the at least one semiconductor die. The insulating portion forms a first external surface of the semiconductor package. The semiconductor package includes at least one through-mold via extending from the first external surface through the insulating portion to at least one of the semiconductor die or the submount.

Abstract: Semiconductor devices and methods are provided. In one example, a semiconductor device includes an active region comprising one or more active semiconductor cells. The semiconductor device includes a metallization structure on the active region. The metallization structure includes beryllium.

Abstract: Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.