Patents by Inventor Devarajan Balaraman
Devarajan Balaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230260861Abstract: Semiconductor packages and, more particularly, semiconductor packages with increased power handling capabilities are disclosed. Semiconductor packages may include lead frame structures and corresponding housings that incorporate semiconductor die. To promote increased current and voltage capabilities, exemplary semiconductor packages include one or more arrangements of creepage extension structures, lead frame structures that may include integral thermal pads, additional thermal elements, and combinations thereof. Creepage extension structures may be arranged as part of top sides of semiconductor packages along with thermal pads of lead frame structures and additional thermal elements. Creepage extension structures may also be arranged as part of top sides and along on one or more peripheral edges of semiconductor packages to promote further increases in power handling.Type: ApplicationFiled: February 11, 2022Publication date: August 17, 2023Inventors: Geza Dezsi, Devarajan Balaraman, Brice McPherson
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Publication number: 20220238426Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate.Type: ApplicationFiled: January 27, 2021Publication date: July 28, 2022Inventors: Sayan Seal, Kuldeep Saxena, Devarajan Balaraman
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Publication number: 20210043465Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.Type: ApplicationFiled: October 27, 2020Publication date: February 11, 2021Inventors: Devarajan Balaraman, Daniel Richter, Greg Hames, Dean Zehnder, Glenn Rinne
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Patent number: 10832921Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.Type: GrantFiled: May 28, 2019Date of Patent: November 10, 2020Assignee: AMKOR TECHNOLOGY, INC.Inventors: Devarajan Balaraman, Daniel Richter, Greg Hames, Dean Zehnder, Glenn Rinne
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Publication number: 20190279882Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Devarajan Balaraman, Daniel Richter, Greg Hames, Dean Zehnder, Glenn Rinne
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Patent number: 10304697Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.Type: GrantFiled: October 5, 2017Date of Patent: May 28, 2019Assignee: Amkor Technology, Inc.Inventors: Devarajan Balaraman, Daniel Richter, Greg Hames, Dean Zehnder, Glenn Rinne
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Publication number: 20190109018Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.Type: ApplicationFiled: October 5, 2017Publication date: April 11, 2019Inventors: Devarajan Balaraman, Daniel Richter, Greg Hames, Dean Zehnder, Glenn Rinne
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Patent number: 10157872Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.Type: GrantFiled: July 13, 2018Date of Patent: December 18, 2018Assignee: Amkor Technology, Inc.Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
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Publication number: 20180323161Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.Type: ApplicationFiled: July 13, 2018Publication date: November 8, 2018Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
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Patent number: 10037957Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.Type: GrantFiled: November 14, 2016Date of Patent: July 31, 2018Assignee: AMKOR TECHNOLOGY, INC.Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
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Publication number: 20180138138Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.Type: ApplicationFiled: November 14, 2016Publication date: May 17, 2018Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
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Patent number: 8456016Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: GrantFiled: March 23, 2010Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Patent number: 8174017Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.Type: GrantFiled: August 16, 2006Date of Patent: May 8, 2012Assignee: Georgia Tech Research CorporationInventors: Markondeya Raj Pulugurtha, Devarajan Balaraman, Isaac R. Abothu, Rao Tummala, Farrokh Ayazi
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Publication number: 20100289154Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: ApplicationFiled: March 23, 2010Publication date: November 18, 2010Inventors: Yonggang Li, Amruthavalll P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Patent number: 7749900Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: GrantFiled: September 30, 2008Date of Patent: July 6, 2010Assignee: Intel CorporationInventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Publication number: 20100078805Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
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Publication number: 20070040204Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.Type: ApplicationFiled: August 16, 2006Publication date: February 22, 2007Inventors: Markondeya Pulugurtha, Devarajan Balaraman, Isaac Abothu, Rao Tummala, Farrokh Ayazi
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Publication number: 20060269762Abstract: Disclosed are organic-compatible thin film processing techniques with reactive (such as Ti) layers for embedding capacitors into substrates. Hydrothermal synthesis allows direct deposition of high-k films with capacitance density of about 1 ?F/cm2 on organic substrates. This is done by reactively growing a high-k film from Ti foil/Ti-coated copper foil/Ti precursor-coated organic substrate in an alkaline barium ion bath. Alternatives may be used to address multiple coatings, low temperature baking, low temperature pyrolysis with oxygen plasma, etc. Sol-gel and RF-sputtering assisted by a reaction with the intermediate layer and a foil transfer process may be used to integrate perovskite thin films with a capacitance in the range of 1-5 ?F/cm2. Thermal oxidation of titanium foil/Ti-coated copper foil/Ti-coated organic substrate with a copper conductive layer is also a reactively grown high-k film process for integrating capacitance of hundreds of nF with or without using a foil transfer process.Type: ApplicationFiled: February 27, 2006Publication date: November 30, 2006Inventors: Markondeya Pulugurtha, Devarajan Balaraman, Rao Tummala, Isaac Abothu