Patents by Inventor Devarshi Mrinal DAS

Devarshi Mrinal DAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof
    Patent number: 11774496
    Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: October 3, 2023
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY
    Inventors: Mahendra Sakare, Puneet Singh, Mayank Kumar Singh, Devarshi Mrinal Das, Vinayak Gopal Hande
  • PSEUDO-RANDOM BINARY SEQUENCES (PRBS) GENERATOR FOR PERFORMING ON-CHIP TESTING AND A METHOD THEREOF
    Publication number: 20220317181
    Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.
    Type: Application
    Filed: January 19, 2022
    Publication date: October 6, 2022
    Inventors: Mahendra SAKARE, Puneet SINGH, Mayank Kumar SINGH, Devarshi Mrinal DAS, Vinayak Gopal HANDE