Abstract: A virtualized controller area network (CAN) system including multiple virtual CAN controllers and a CAN virtual network controller. The CAN virtual network controller includes virtual CAN interfaces, network interfaces, and a configuration controller. Each of the virtual CAN interfaces communicatively links each virtual CAN controller with the network interfaces, which are each configured to communicatively link one or more of virtual CAN controllers into a CAN network. The configuration controller programs any one or more of the network interfaces to communicatively link any one or more of the virtual CAN controllers in each of one or more CAN networks. The configuration controller configures a network interface for virtual communications for implementing a virtual CAN network, or enables a linked physical protocol engine for implementing a physical CAN network. The number of protocol engines needed, if any, may be significantly reduced thereby reducing pin count and silicon area consumption.

Abstract: A controller area network (CAN) node is described for determining a bus load on a CAN bus. An indication of a time window duration of a time window is received by the CAN node and a start time for determining a bus load and an end time based on the start time and the time window duration is defined. The bus load is based on determining whether the CAN bus is active for each bit of one or more bits detected on the CAN bus between the start time and the end time. The bus load is compared to a threshold range. A signal is sent to a host processor if the bus load exceeds or falls below the threshold range.

Abstract: A virtualized controller area network (CAN) system including multiple virtual CAN controllers and a CAN virtual network controller. The CAN virtual network controller includes virtual CAN interfaces, network interfaces, and a configuration controller. Each of the virtual CAN interfaces communicatively links each virtual CAN controller with the network interfaces, which are each configured to communicatively link one or more of virtual CAN controllers into a CAN network. The configuration controller programs any one or more of the network interfaces to communicatively link any one or more of the virtual CAN controllers in each of one or more CAN networks. The configuration controller configures a network interface for virtual communications for implementing a virtual CAN network, or enables a linked physical protocol engine for implementing a physical CAN network. The number of protocol engines needed, if any, may be significantly reduced thereby reducing pin count and silicon area consumption.

Abstract: Systems and methods for debugging multi-core processors with configurable isolated partitions have been described. In an illustrative, non-limiting embodiment, an integrated circuit, may include: a plurality of Cross-Trigger Matrices (CTMs) configured to establish a debug network among a plurality of multi-cluster tiles (MCTs), where each MCT includes a plurality of processor cores, and where each processor core is assigned to a respective isolated partition of processor cores; and a System Interface (SI) coupled to the plurality of CTMs, where the SI is configured to control the plurality of CTMs to enable or disable at least a portion of the debug network to allow an isolated partition to be debugged independently of another isolated partition. A method may include enabling or disabling, by the SI, buses between the MCTs to create isolated debug networks, each isolated debug network corresponding to a distinct isolated partition of processor cores.

Abstract: A controller area network (CAN) node is described for determining a bus load on a CAN bus. An indication of a time window duration of a time window is received by the CAN node and a start time for determining a bus load and an end time based on the start time and the time window duration is defined. The bus load is based on determining whether the CAN bus is active for each bit of one or more bits detected on the CAN bus between the start time and the end time. The bus load is compared to a threshold range. A signal is sent to a host processor if the bus load exceeds or falls below the threshold range.

Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.

Abstract: Methods and circuits in an application circuit to compensate for skew in the transmission of serial data between field programmable gate arrays (FPGAs) in the application circuit. A clock signal source external to both FPGAs generates a clock signal applied to both FPGAs. A transmitting FPGA generates a serial data stream comprising the current values of a plurality of signals within the transmitting FPGA and transmits the serial data stream based on its clock signal. The receiving FPGA receives the serial data stream and applies a programmed delay to the received serial data stream to compensate for skew in received serial data stream relative to its clock signal. The programmed delay value may be determined at initialization (or reset) of the FPGAs by transmitting synchronization data from the first transmitting FPGA to the receiving FPGA. The receiving FPGA adjusts a programmable delay while receiving synchronization data until it sense bit and word alignment relative to its clock signal.