Patents by Inventor Devendra Kumar Sadana

Devendra Kumar Sadana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7550369
    Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventors: Joel Pereira de Souza, Keith Edward Fogel, John Albrecht Ott, Devendra Kumar Sadana, Katherine Lynn Saenger
  • Patent number: 7524740
    Abstract: A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Devendra Kumar Sadana, Kern Rim
  • Patent number: 7504311
    Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven John Koester, Devendra Kumar Sadana, Ghavam G. Shahidi
  • Patent number: 7492008
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
  • Patent number: 7285473
    Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Joel Pereira de Souza, Keith Edward Fogel, John Albrecht Ott, Devendra Kumar Sadana, Katherine Lynn Saenger
  • Patent number: 7282425
    Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Steven John Koester, Devendra Kumar Sadana, Ghavam G. Shahidi
  • Patent number: 6784072
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
  • Patent number: 6756257
    Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: June 29, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bijan Davari, Devendra Kumar Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Publication number: 20040013886
    Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Applicant: International Business Machines Corporation
    Inventors: Stephen Richard Fox, Neena Garg, Kenneth John Giewont, Junedong Lee, Siegfried Lutz Maurer, Dan Moy, Maurice Heathcote Norcott, Devendra Kumar Sadana
  • Publication number: 20030104681
    Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.
    Type: Application
    Filed: October 11, 2001
    Publication date: June 5, 2003
    Inventors: Bijan Davari, Devendra Kumar Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Publication number: 20020115240
    Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 22, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward Joseph Nowak, Devendra Kumar Sadana, Ghavam G. Shahidi
  • Patent number: 6432754
    Abstract: The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward Joseph Nowak, Devendra Kumar Sadana, Ghavam G. Shahidi
  • Patent number: 6333532
    Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Bijan Davari, Devendra Kumar Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Patent number: 6300218
    Abstract: A method of forming a patterned buried oxide film, includes performing an implantation into a substrate, forming a mask on at least portions of the substrate for controlling the implantation diffusion, and annealing the substrate to form a buried oxide. The mask may be selectively patterned. A region that is covered by the mask has a thinner buried oxide than an area which is exposed directly to the annealing ambient.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: October 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: Guy Moshe Cohen, Devendra Kumar Sadana
  • Patent number: 6259137
    Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corp.
    Inventors: Devendra Kumar Sadana, Joel P. de Souza
  • Patent number: 6222253
    Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200° C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventors: Devendra Kumar Sadana, Orin Wayne Holland
  • Patent number: 6204546
    Abstract: An SOI substrate and method of forming is described incorporating the steps of implanting oxygen under two conditions and performing two high temperature anneals at temperatures above 1250° C. and above 1300° C., respectively, at two respective oxygen concentrations. The invention overcomes the problem of high SOI substrate fabrication cost due to ion implant time and of getting high quality buried oxide (BOX) layers below a thin layer of single crystal silicon.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter Roitman, Devendra Kumar Sadana
  • Patent number: 6090689
    Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: July 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Devendra Kumar Sadana, Orin Wayne Holland
  • Patent number: 6087242
    Abstract: A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: July 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Humphrey John Maris, Devendra Kumar Sadana
  • Patent number: 6043166
    Abstract: An SOI substrate and method of forming is described incorporating the steps of implanting oxygen under two conditions and performing two high temperature anneals at temperatures above 1250.degree. C. and above 1300.degree. C., respectively, at two respective oxygen concentrations. The invention overcomes the problem of high SOI substrate fabrication cost due to ion implant time and of getting high quality buried oxide (BOX) layers below a thin layer of single crystal silicon.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: March 28, 2000
    Assignees: International Business Machines Corporation, The United States of America as represented by the Department of Commerce
    Inventors: Peter Roitman, Devendra Kumar Sadana