Abstract: A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A bit line that has a feedback path from the bit line to a storage cell on the bit line is provided. The feedback path allows the bit line to discharge through a discharge device that is connected to a non-discharging local bit line. Further, a discharge device capable of discharging a global bit line even when a storage cell connected to the discharge device is not being evaluated is provided. Further, a method to perform a memory array operation by discharging a bit line using multiple discharge devices is provided.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Abstract: A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.