Patents by Inventor Devendra Sadana
Devendra Sadana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060151787Abstract: A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the underlying relaxed SiGe substrate. In accordance with the present invention, the SiGe buffer layer has a Ge content that is less than the Ge content which is present in the relaxed SiGe substrate.Type: ApplicationFiled: January 12, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huajie Chen, Anda Mocuta, Stephen Bedell, Effendi Leobandung, Devendra Sadana
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Publication number: 20060148143Abstract: A method of forming a surface Ge-containing channel which can be used to fabricate a Ge-based field effect transistor (FET) which can be applied to semiconductor-on-insulator substrates (SOIs) is provided. The disclosed method uses Ge-containing ion beams, such as cluster ion beams, to create a strained Ge-containing rich region at or near a surface of a SOI substrate. The Ge-containing rich region can be present continuously across the entire surface of the semiconductor substrate, or it can be present as a discrete region at a predetermined surface portion of the semiconductor substrate.Type: ApplicationFiled: January 6, 2005Publication date: July 6, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Bruce Doris, Devendra Sadana
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Publication number: 20060105507Abstract: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.Type: ApplicationFiled: November 18, 2004Publication date: May 18, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Meikei Ieong, Devendra Sadana, Ghavam Shahidi
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Publication number: 20060105559Abstract: A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from about 100 angstroms to about 1 micron and annealing the substrate at a temperature from 1200° C. to 1400°0 C. in an oxygen containing atmosphere. The invention over comes the problem of the buried oxide breaking up into oxide islands during the anneal.Type: ApplicationFiled: November 15, 2004Publication date: May 18, 2006Applicant: International Business Machines CorporationInventors: Tze-Chiang Chen, Bernard Meyerson, Devendra Sadana
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Publication number: 20060081837Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.Type: ApplicationFiled: December 2, 2005Publication date: April 20, 2006Applicant: International Business Machines CorporationInventors: Stephen Bedell, Anthony Domenicucci, Keith Fogel, Effendi Leobandung, Devendra Sadana
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Publication number: 20060057403Abstract: High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 ? or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.Type: ApplicationFiled: November 7, 2005Publication date: March 16, 2006Applicant: International Business Machines CorporationInventors: Stephen Bedell, Huajie Chen, Keith Fogel, Devendra Sadana
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Publication number: 20060042542Abstract: A method of fabricating a high-quality relaxed SiGe-on-insulator substrate material is provided in which a prefabricated silicon-on-insulator substrate is first exposed to an unstrained Ge-containing source and then heated (annealed/oxidized) to cause Ge diffusion and thermal mixing of Ge within a single-crystal Si-containing layer of the prefabricated silicon-on-insulator substrate. The unstrained Ge-containing source can comprise a solid Ge-containing source, a gaseous Ge-containing source, or ions of Ge.Type: ApplicationFiled: September 2, 2004Publication date: March 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Keith Fogel, Devendra Sadana
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Publication number: 20060040476Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.Type: ApplicationFiled: August 20, 2004Publication date: February 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Devendra Sadana, Dominic Schepis, Michael Steigerwalt
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Publication number: 20060027808Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 ? thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge.Type: ApplicationFiled: August 5, 2004Publication date: February 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Huajie Chen, Keith Fogel, Ryan Mitchell, Devendra Sadana
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Publication number: 20060030133Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: ApplicationFiled: August 19, 2005Publication date: February 9, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Agnello, Stephen Bedell, Robert Dennard, Anthony Domenicucci, Keith Fogel, Devendra Sadana
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Publication number: 20060024931Abstract: This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance.Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Chan, Joel de Souza, Alexander Reznicek, Devendra Sadana, Katherine Saenger
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Publication number: 20060011906Abstract: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.Type: ApplicationFiled: July 14, 2004Publication date: January 19, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Huajie Chen, Keith Fogel, Devendra Sadana, Ghavam Shahidi
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Publication number: 20060001089Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.Type: ApplicationFiled: July 2, 2004Publication date: January 5, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Anthony Domenicucci, Keith Fogel, Effendi Leobandung, Devendra Sadana
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Publication number: 20060003555Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.Type: ApplicationFiled: July 2, 2004Publication date: January 5, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Adam, Stephen Bedell, Joel de Souza, Keith Fogel, Alexander Reznicek, Devendra Sadana, Ghavam Shahidi
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Publication number: 20050236687Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.Type: ApplicationFiled: April 22, 2004Publication date: October 27, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Chan, Bruce Doris, Kathryn Guarini, Meikei Ieong, Shreesh Narasimha, Alexander Reznicek, Kern Rim, Devendra Sadana, Leathen Shi, Jeffrey Sleight, Min Yang
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Publication number: 20050221591Abstract: A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.Type: ApplicationFiled: April 6, 2004Publication date: October 6, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Huajie Chen, Joel de Souza, Keith Fogel, Devendra Sadana, Ghavam Shahidi
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Publication number: 20050208780Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.Type: ApplicationFiled: January 5, 2005Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bedell, Anthony Domenicucci, Keith Fogel, Devendra Sadana
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Publication number: 20050170570Abstract: A SIMOX (separation by implanted oxygen) process is provided that forms a silicon-on-insulator (SOI) substrate having a buried oxide with improved electrical properties. The process implements at least one of the following processing steps into SIMOX: (I) lowering of the oxygen ion dose in the base oxygen ion implant step; (II) off-setting the implant energy of the room temperature (RT) implant step to a value that is about 5 to about 20% lower than the base ion implant step; and (III) creating a soak cycle, i.e., pre-annealing step, prior to the internal oxidation anneal which allows dissolution of Si and SiOx precipitates in the oxygen implanted region. The temperature and time of the soak cycle as well as the base implant dose are critical in determining the final BOX quality.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel DeSouza, Keith Fogel, Harold Hovel, Junedong Lee, Siegfried Maurer, Devendra Sadana, Dominic Schepis
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Publication number: 20050153487Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.Type: ApplicationFiled: January 19, 2005Publication date: July 14, 2005Applicant: International Business Machines CorporationInventors: Stephen Bedell, Joel de Souza, Keith Fogel, Devendra Sadana, Ghavam Shahidi
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Publication number: 20050148162Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface.Type: ApplicationFiled: January 2, 2004Publication date: July 7, 2005Inventors: Huajie Chen, Dan Mocuta, Richard Murphy, Stephen Bedell, Devendra Sadana