Abstract: The present disclosure relates generally to natural language understanding.

Abstract: The present disclosure relates generally to natural language understanding.

Abstract: A method for facilitating the assignment of alternating voltage potentials to a set of shield wires in a routing layer of an integrated circuit involves generating a set of vertices representing at least a portion of the set of shield wires and of edges representing adjacency of at least the portion of the set of shield wires, minimizing a set of edges in the set of vertices to obtain a minimized set of vertices, and assigning a first indicator to one vertex of the minimized set of vertices.

Abstract: A method for creating a wire load model using specific interconnect configuration information is provided. Further, a program that creates a wire load model by curve-interconnect fitting parasitic information and interconnect configuration information is provided. Further, a computer system capable of creating an accurate wire load model using parasitic information specific to particular metal layers is provided.

Abstract: A method for facilitating the assignment of alternating voltage potentials to a set of shield wires in a routing layer of an integrated circuit involves generating a set of vertices representing at least a portion of the set of shield wires and of edges representing adjacency of at least the portion of the set of shield wires, minimizing a set of edges in the set of vertices to obtain a minimized set of vertices, and assigning a first indicator to one vertex of the minimized set of vertices.

Abstract: A technique for verifying decoupling capacitance using a maximum flow determination is provided. The technique involves generating a network representing decoupling capacitors and driver elements on an integrated circuit, selectively establishing connections between decoupling capacitors and driver elements, and determining a maximum flow of the network. Using the maximum flow of the network, a designer may then verify whether particular driver elements are receiving sufficient decoupling capacitance and whether particular decoupling capacitors are being used efficiently, and subsequently redesign an integrated circuit as deemed necessary.

Abstract: A technique for verifying on-chip decoupling capacitance using transistor and capacitor surface area information is provided. The technique broadly includes determining a surface area of a transistor, determining a surface area of a decoupling capacitor, comparing the surface area of the transistor to the surface area of the decoupling capacitor to obtain a surface area ratio, and verifying whether there is enough decoupling capacitance based on the surface area ratio. Further, the present invention also provides a technique for determining when and how to redesign a microprocessor in order to have sufficient decoupling capacitance.

Abstract: A technique for verifying decoupling capacitance using a maximum flow determination is provided. The technique involves generating a network representing decoupling capacitors and driver elements on an integrated circuit, selectively establishing connections between decoupling capacitors and driver elements, and determining a maximum flow of the network. Using the maximum flow of the network, a designer may then verify whether particular driver elements are receiving sufficient decoupling capacitance and whether particular decoupling capacitors are being used efficiently, and subsequently redesign an integrated circuit as deemed necessary.

Abstract: A technique for verifying on-chip decoupling capacitance using transistor and capacitor surface area information is provided. The technique broadly includes determining a surface area of a transistor, determining a surface area of a decoupling capacitor, comparing the surface area of the transistor to the surface area of the decoupling capacitor to obtain a surface area ratio, and verifying whether there is enough decoupling capacitance based on the surface area ratio. Further, the present invention also provides a technique for determining when and how to redesign a microprocessor in order to have sufficient decoupling capacitance.

Abstract: A method for finding a worst case aggressor set of a victim net based on logically exclusive sets is provided. Further, a software tool that finds a worst case aggressor set of a victim net based on logically exclusive sets is provided. Further, a method for formulating a problem to find a worst case aggressor net of a victim net based on a logically exclusive set is provided. Further, a software tool for formulating a problem to find a worst case aggressor net of a victim net based on a logically exclusive set is provided. Further, a method for solving a problem to find a worst case aggressor net based on logically exclusive sets is provided. Further, a software tool for solving a problem to find a worst case aggressor net based on a logically exclusive net is provided.