Patents by Inventor Devereaux C. Chen
Devereaux C. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8170028Abstract: A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.Type: GrantFiled: July 29, 2009Date of Patent: May 1, 2012Assignee: Juniper Networks, Inc.Inventors: Dennis C Ferguson, Hann-Hwan Ju, Atsushi Kasuya, Gerald Cheung, Devereaux C Chen
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Patent number: 8131950Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.Type: GrantFiled: April 29, 2011Date of Patent: March 6, 2012Assignee: Juniper Networks, Inc.Inventors: Devereaux C. Chen, Jeffrey R. Zimmer
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Publication number: 20110208926Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Devereaux C. CHEN, Jeffrey R. ZIMMER
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Patent number: 8004980Abstract: A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance.Type: GrantFiled: March 26, 2010Date of Patent: August 23, 2011Assignee: Juniper Networks, Inc.Inventors: Dennis C Ferguson, Devereaux C Chen, John W Stewart, III, James Washburn, Jeffrey R Zimmer
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Patent number: 8001335Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.Type: GrantFiled: September 9, 2010Date of Patent: August 16, 2011Assignee: Juniper Networks, Inc.Inventors: Devereaux C. Chen, Jeffrey R. Zimmer
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Patent number: 7986717Abstract: A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET. The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.Type: GrantFiled: June 26, 2009Date of Patent: July 26, 2011Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Devereaux C. Chen, Eric M. Verwillow, Ramesh Padmanabhan, Thomas Michael Skibo
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Publication number: 20110010474Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.Type: ApplicationFiled: September 9, 2010Publication date: January 13, 2011Applicant: JUNIPER NETWORKS, INC.Inventors: Devereaux C. CHEN, Jeffrey R. Zimmer
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Patent number: 7814283Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.Type: GrantFiled: February 27, 2006Date of Patent: October 12, 2010Assignee: Juniper Networks, Inc.Inventors: Devereaux C. Chen, Jeffrey R. Zimmer
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Publication number: 20100177638Abstract: A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance.Type: ApplicationFiled: March 26, 2010Publication date: July 15, 2010Applicant: JUNIPER NETWORKS, INC.Inventors: Dennis C. Ferguson, Devereaux C. Chen, John W. Stewart, III, James Washburn, Jeffrey R. Zimmer
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Patent number: 7715315Abstract: A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance.Type: GrantFiled: April 27, 2007Date of Patent: May 11, 2010Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Devereaux C. Chen, John W. Stewart, III, James Washburn, Jeffrey R. Zimmer
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Publication number: 20090257459Abstract: A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET, The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets. sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.Type: ApplicationFiled: June 26, 2009Publication date: October 15, 2009Applicant: JUNIPER NETWORKS, INC.Inventors: Dennis C. FERGUSON, Devereaux C. CHEN, Eric M. VERWILLOW, Ramesh PADMANABHAN, Thomas Michael SKIBO
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Patent number: 7586917Abstract: A network device includes an input interface, at least one processing path and an output interface. The input interface receives data units on a plurality of streams and assigns a first sequence number to each of the received data units. The at least one processing path performs a route look-up for each of the data units, where the route look-up determines a routing destination for a respective data unit. The output interface assigns a second sequence number to each of the processed data units based on a number of memory references associated with the route look-up for each of the data units and re-orders the processed data units based on the second sequence number assigned to each of the processed data units.Type: GrantFiled: May 19, 2004Date of Patent: September 8, 2009Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Hann-Hwan Ju, Atsushi Kasuya, Gerald Cheung, Devereaux C. Chen
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Patent number: 7570667Abstract: A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET. The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.Type: GrantFiled: July 13, 2006Date of Patent: August 4, 2009Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Devereaux C. Chen, Eric M. Verwillow, Ramesh Padmanabhan, Thomas Michael Skibo
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Patent number: 7227840Abstract: A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance.Type: GrantFiled: March 18, 2002Date of Patent: June 5, 2007Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Devereaux C. Chen, John W. Stewart, III, James Washburn, Jeffrey R. Zimmer
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Patent number: 7099352Abstract: A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET. The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler.Type: GrantFiled: January 3, 2001Date of Patent: August 29, 2006Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Devereaux C. Chen, Eric M. Verwillow, Ramesh Padmanabhan, Thomas Michael Skibo
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Patent number: 7039770Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.Type: GrantFiled: March 5, 2002Date of Patent: May 2, 2006Assignee: Juniper Networks, Inc.Inventors: Devereaux C. Chen, Jeffrey R. Zimmer
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Patent number: 7009416Abstract: A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.Type: GrantFiled: October 29, 2001Date of Patent: March 7, 2006Assignee: Juniper Networks, Inc.Inventors: Tatao Chuang, Devereaux C. Chen
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Patent number: 6810501Abstract: A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one another. The system also receives a signal representing a quantity of valid portions in the data and a current CRC value. The system updates the current CRC value using the data and signal in a single clock cycle.Type: GrantFiled: January 3, 2001Date of Patent: October 26, 2004Assignee: Juniper Networks, Inc.Inventors: Dennis C. Ferguson, Devereaux C. Chen, Ramesh Padmanabhan, Chang-Hong Wu, Thomas Michael Skibo
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Patent number: 5121186Abstract: A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon in to an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.Type: GrantFiled: October 23, 1990Date of Patent: June 9, 1992Assignee: Hewlett-Packard CompanyInventors: Siu-Weng S. Wong, Devereaux C. Chen, Kuang-Yi Chiu
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Patent number: 4873204Abstract: A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon into an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.Type: GrantFiled: November 8, 1988Date of Patent: October 10, 1989Assignee: Hewlett-Packard CompanyInventors: Siu-Weng S. Wong, Devereaux C. Chen, Kuang-Yi Chiu