Patents by Inventor Devesh Kumar Datta
Devesh Kumar Datta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072159Abstract: A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Manoj Chandrika Reghunathan, Devesh Kumar Datta, Eric Alois Graetz, Muhammad Akmal Hasanudin, Vijay Anand Ramadass
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Publication number: 20230197846Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate and transistor cells electrically coupled in parallel to form a power transistor. Each transistor cell includes a source region in a silicon layer of the SOI substrate, a body region in the silicon layer and adjoining the source region, a gate structure configured to control a channel within the body region, a drain region in the silicon layer, and a drift region laterally separating the body region from the drain region. Each gate structure includes a gate electrode separated from the silicon layer by a gate dielectric having a thickness in a range of 20 nm to 60 nm. An effective length of the channel of each transistor cell is in a range of 50 nm to 500 nm. The power transistor has a maximum rated voltage in a range of 5V to 60V. Corresponding methods of producing the semiconductor device are also described.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Manoj Chandrika Reghunathan, Devesh Kumar Datta, Eric Graetz, Soon Huat Niew
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Publication number: 20210091009Abstract: Some embodiments include a memory device having a conductive structure which includes silicon-containing material. A stack is over the conductive structure and includes alternating insulative levels and conductive levels. Channel material pillars extend through the stack and are electrically coupled with the conductive structure. Memory cells are along the channel material pillars. A conductive barrier material is under the silicon-containing material. The conductive barrier material includes one or more metals in combination with one or more nonmetals. An electrical contact is under the conductive barrier material. The electrical contact includes a region reactive with silicon. Silicon is precluded from reaching said region at least in part due to the conductive barrier material. Control circuitry is under the electrical contact and is electrically coupled with the conductive structure through at least the electrical contact and the conductive barrier material.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Applicant: Micron Technology, Inc.Inventors: Devesh Kumar Datta, David Daycock, Keen Wah Chow, Tom George, Justin B. Dorhout, Bingli Ma, Rita J. Klein, John Mark Meldrim
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Patent number: 10475810Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: June 29, 2018Date of Patent: November 12, 2019Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Publication number: 20180308861Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Applicant: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Patent number: 10014319Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: August 17, 2017Date of Patent: July 3, 2018Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Patent number: 9773807Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: March 10, 2017Date of Patent: September 26, 2017Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Publication number: 20130234280Abstract: A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time.Type: ApplicationFiled: March 16, 2012Publication date: September 12, 2013Applicant: INOTERA MEMORIES, INC.Inventors: ARVIND KUMAR, ERIC LAHAUG, DEVESH KUMAR DATTA, KEEN WAH CHOW, CHIA MING YANG, CHIEN-CHI LEE, FREDERICK DAVID FISHBURN
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Publication number: 20110201185Abstract: Methods to dope transistors with equal or similar dopant concentration are described. In a first alternative, a slow dose per pulse ramp during plasma-assisted doping is proposed. This method results in a thinner surface deposited layer resulting in equal dopant concentration throughout the area. In a second alternative, transistors are placed away from the mask edge in order to achieve equal dopant concentration.Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Inventors: Devesh Kumar Datta, Keen Wah Chow, Chun Kit Kwok, Wai Khin Joshua Lee
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Patent number: 7407871Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena.Type: GrantFiled: September 5, 2006Date of Patent: August 5, 2008Assignee: TECH Semiconductor Singapore Pte LtdInventors: Arvind Kumar, Keen Wah Chow, Devesh Kumar Datta, Subramanian Krishnan
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Publication number: 20080124814Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena.Type: ApplicationFiled: September 5, 2006Publication date: May 29, 2008Inventors: Arvind Kumar, Keen Wah Chow, Devesh Kumar Datta, Subramanian Krishnan