Patents by Inventor Devin Batutis
Devin Batutis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418475Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Inventors: Pitamber Shukla, Ching-Huang Lu, Devin Batutis
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Patent number: 11823748Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.Type: GrantFiled: August 18, 2022Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley
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Publication number: 20230195355Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.Type: ApplicationFiled: April 29, 2022Publication date: June 22, 2023Inventors: Pitamber Shukla, Avinash Rajagiri, Devin Batutis
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Publication number: 20220392547Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.Type: ApplicationFiled: August 18, 2022Publication date: December 8, 2022Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N. Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley
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Patent number: 11437108Abstract: A difference between a current temperature and a prior temperature of a memory device is determined. In response to a determination that the difference between the current temperature and the prior temperature of the memory device satisfies a temperature criterion, an amount of voltage shift is measured for a set of memory cells of a block family associated with a first voltage bin of a set of voltage bins at the memory device. The first voltage bin is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the set of memory cells based on the determined amount of voltage shift and a temporary voltage shift offset associated with the difference between the current temperature and the prior temperature for the memory device. In response to a determination that the adjusted amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the set of voltage bins.Type: GrantFiled: April 14, 2021Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Karl Schuh, Mustafa N Kaynak, Xiangang Luo, Shane Nowell, Devin Batutis, Sivagnanam Parthasarathy, Sampath Ratnam, Jiangang Wu, Peter Feeley
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Patent number: 11288149Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.Type: GrantFiled: October 7, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
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Publication number: 20210019241Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.Type: ApplicationFiled: October 7, 2020Publication date: January 21, 2021Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
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Patent number: 10824527Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: GrantFiled: July 5, 2019Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
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Patent number: 10685731Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.Type: GrantFiled: May 13, 2019Date of Patent: June 16, 2020Assignee: Micron Technology, Inc.Inventors: Ting Luo, Scott Anthony Stoller, Preston Allen Thomson, Devin Batutis, Harish Reddy Singidi, Kulachet Tanpairoj
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Publication number: 20200005884Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.Type: ApplicationFiled: May 13, 2019Publication date: January 2, 2020Inventors: Ting Luo, Scott Anthony Stoller, Preston Allen Thomson, Devin Batutis, Harish Reddy Singidi, Kulachet Tanpairoj
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Publication number: 20190324876Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: ApplicationFiled: July 5, 2019Publication date: October 24, 2019Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
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Patent number: 10387281Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: GrantFiled: August 30, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Thomson
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Patent number: 10325670Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.Type: GrantFiled: September 12, 2018Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Ting Luo, Scott Anthony Stoller, Preston Thomson, Devin Batutis, Harish Reddy Singidi, Kulachet Tanpairoj
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Publication number: 20190066817Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.Type: ApplicationFiled: September 12, 2018Publication date: February 28, 2019Inventors: Ting Luo, Scott Anthony Stoller, Preston Thomson, Devin Batutis, Harish Reddy Singidi, Kulachet Tanpairoj
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Publication number: 20190065331Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Harish Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Thomson
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Patent number: 10096380Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.Type: GrantFiled: August 31, 2017Date of Patent: October 9, 2018Assignee: Micron Technology, Inc.Inventors: Ting Luo, Scott Anthony Stoller, Preston Thomson, Devin Batutis, Harish Singidi, Kulachet Tanpairoj
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Patent number: 6684173Abstract: The present invention provides a screen for abnormal cells using the cell transconductance. In one embodiment, a method involves reading cells against an elevated reference current while applying an elevated gate voltage, or alternatively, reading all cells against a standard reference current while applying a nominal or elevated gate voltage, and a reduced drain voltage. The abnormal cells fail this test while normal cells pass.Type: GrantFiled: October 9, 2001Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventors: Jeffrey Alan Kessenich, Andrei Mihnea, Devin Batutis
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Publication number: 20030074152Abstract: The present invention provides a screen for abnormal cells using the cell transconductance. In one embodiment, a method involves reading cells against an elevated reference current while applying an elevated gate voltage, or alternatively, reading all cells against a standard reference current while applying a nominal or elevated gate voltage, and a reduced drain voltage. The abnormal cells fail this test while normal cells pass.Type: ApplicationFiled: October 10, 2001Publication date: April 17, 2003Inventors: Jeffrey Alan Kessenich, Andrei Mihnea, Devin Batutis