Patents by Inventor Devin Bayles

Devin Bayles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single event upset immune keeper circuit and method for dual redundant dynamic logic
    Patent number: 7075337
    Abstract: A method includes precharging a first dynamic node, precharging a second dynamic node, and maintaining a first logic state of a signal on the first dynamic node responsive to a second logic state of a signal on the second dynamic node. The method further includes maintaining the second logic state of the signal on the second dynamic node responsive to the first logic state of the signal on the first dynamic node.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 11, 2006
    Assignee: BAE SYSTEMS Information and Electronic Systems Integration, Inc.
    Inventors: Neil Edward Wood, Devin Bayles
  • Single event upset immune keeper circuit and method for dual redundant dynamic logic
    Publication number: 20060001442
    Abstract: A method includes precharging a first dynamic node, precharging a second dynamic node, and maintaining a first logic state of a signal on the first dynamic node responsive to a second logic state of a signal on the second dynamic node. The method further includes maintaining the second logic state of the signal on the second dynamic node responsive to the first logic state of the signal on the first dynamic node.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Neil Wood, Devin Bayles
  • Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements
    Patent number: 6948145
    Abstract: A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process. The tool suite facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through a cell, and auditing cells for errors prior to inclusion in a manufacturing library.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: September 20, 2005
    Assignee: BAE Systems and Information and Electronic Integration, Inc.
    Inventors: Arnett J. Brown, III, Robert J. Stalker, Rajen Naran Lakhani, Eric Wayne Neiderer, Devin Bayles
  • Tool suite for the rapid development of advanced standard cell libraries
    Publication number: 20030121019
    Abstract: A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process. The tool suit facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through a cell, and auditing cells for errors prior to inclusion in a manufacturing library.
    Type: Application
    Filed: February 14, 2003
    Publication date: June 26, 2003
    Inventors: Arnett J. Brown, Robert J. Stalker, Rajen Naran Lakhani, Eric Wayne Neiderer, Devin Bayles
  • Tool suite for the rapid development of advanced standard cell libraries
    Patent number: 6539533
    Abstract: A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process. The tool suit facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through a cell, and auditing cells for errors prior to inclusion in a manufacturing library.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: March 25, 2003
    Assignee: BAE Systems Information and Electronic Systems Integration, Inc.
    Inventors: Arnett J. Brown, III, Robert J. Stalker, Rajen Naran Lakhani, Eric Wayne Neiderer, Devin Bayles