Patents by Inventor Devin M. Batutis
Devin M. Batutis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966616Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.Type: GrantFiled: February 27, 2023Date of Patent: April 23, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
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Patent number: 11886336Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.Type: GrantFiled: January 31, 2023Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Mustafa N. Kaynak, Devin M. Batutis, Xiangang Luo
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Patent number: 11837307Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.Type: GrantFiled: November 2, 2022Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Publication number: 20230325273Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.Type: ApplicationFiled: June 8, 2023Publication date: October 12, 2023Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Patent number: 11783901Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.Type: GrantFiled: August 4, 2022Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo
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Patent number: 11709727Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.Type: GrantFiled: March 30, 2021Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Publication number: 20230205447Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
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Publication number: 20230176963Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.Type: ApplicationFiled: January 31, 2023Publication date: June 8, 2023Inventors: Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Mustafa N. Kaynak, Devin M. Batutis, Xiangang Luo
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Publication number: 20230122275Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley, Devin M. Batutis, Jiangang Wu, Sampath K. Ratnam, Shane Nowell, Karl D. Schuh
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Patent number: 11620074Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.Type: GrantFiled: March 16, 2021Date of Patent: April 4, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell
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Patent number: 11609846Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.Type: GrantFiled: September 11, 2020Date of Patent: March 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Mustafa N. Kaynak, Devin M. Batutis, Xiangang Luo
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Patent number: 11587639Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.Type: GrantFiled: March 11, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley, Devin M. Batutis, Jiangang Wu, Sampath K Ratnam, Shane Nowell, Karl D. Schuh
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Publication number: 20230046724Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing, on data residing in a block of the memory device, an error-handling operation of a plurality of error-handling operations, wherein an order of the plurality of error-handling operations is based on a voltage offset bin associated with the block, wherein the voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations; and responsive to determining that the error-handling operation has failed to recover the data, adjusting the order of the plurality of error-handling operations.Type: ApplicationFiled: November 2, 2022Publication date: February 16, 2023Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Patent number: 11532373Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.Type: GrantFiled: March 18, 2021Date of Patent: December 20, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Publication number: 20220375530Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo
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Patent number: 11501840Abstract: A method is described that includes determining, by a memory subsystem controller of a memory device, a number of memory cells from a set of memory cells that are in a programmed state. The memory subsystem controller further compares the number of memory cells from the set of memory cells that are in the programmed state to a proximity disturb threshold and in response to determining that the number satisfies the proximity disturb threshold, performs a remediation operation on user data stored in the set of memory cells.Type: GrantFiled: April 28, 2021Date of Patent: November 15, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Chun Sum Yeung, Devin M. Batutis
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Publication number: 20220351788Abstract: A method is described that includes determining, by a memory subsystem controller of a memory device, a number of memory cells from a set of memory cells that are in a programmed state. The memory subsystem controller further compares the number of memory cells from the set of memory cells that are in the programmed state to a proximity disturb threshold and in response to determining that the number satisfies the proximity disturb threshold, performs a remediation operation on user data stored in the set of memory cells.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Inventors: Chun Sum Yeung, Devin M. Batutis
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Publication number: 20220318086Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.Type: ApplicationFiled: March 30, 2021Publication date: October 6, 2022Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Patent number: 11456043Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.Type: GrantFiled: April 13, 2021Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Devin M. Batutis, Avinash Rajagiri, Sheng-Huang Lee, Chun Sum Yeung, Harish R. Singidi
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Publication number: 20220300186Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.Type: ApplicationFiled: March 16, 2021Publication date: September 22, 2022Inventors: Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Peter Feeley, Sivagnanam Parthasarathy, Sampath Ratnam, Shane Nowell