Abstract: A system and method for in a communication system is provided. The system includes logic for obtaining a symbol width by examining transition bit values for at least three symbols, wherein if the transition bit values are of same polarity as a central data symbol then the symbol width is too wide, or if the transition bits are of opposite polarity, then the symbol is too narrow. The method includes, determining whether received symbols are too wide or narrow with respect to a clock signal by examining transition bit values for at least three symbols, wherein if the transition bit values are of same polarity as a central data symbol then the symbol width is too wide, or if the transition bits are of opposite polarity, then the symbol is too narrow; and adjusting equalization coefficient values if the symbols are wide or narrow.

Abstract: A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

Abstract: A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.