Abstract: A multi-surface compliant heat removal process that includes identifying components to share a heat rejecting device; applying non-adhesive film to the components; identifying a primary component of the components; and applying phase change material on each of the components, other than the primary component. The phase change material is placed on top of the non-adhesive film. The process also includes placing the heat rejecting device on the corresponding components and removing the heat rejecting device from the corresponding components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device; removing the non-adhesive film from the heat rejecting device; placing a heatsink-attach thermal interface material on the components; and placing the heat rejecting device on the corresponding components.

Abstract: Methods, systems, and software for accepting bets on contests, such as sporting events, with wagering terms that change in real-time with the progress of the contests are disclosed. The disclosed methods, systems, and software may include security features that check the time at which bets are placed to ensure that they are not being placed in the interval between when an event occurred in the contest and when the wagering terms were changed to reflect that the event occurred.

Abstract: A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device; applying non-adhesive film to the one or more components; identifying a primary component of the one or more components; and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components; and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device.

Abstract: A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device, applying non-adhesive film to the one or more components, identifying a primary component of the one or more components, and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device.

Abstract: A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device; applying non-adhesive film to the one or more components; identifying a primary component of the one or more components; and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components; and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device.

Abstract: A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.

Abstract: An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a heat sink with an integrally formed depending skirt, and a conductive, compressible polymer is applied to a bottom surface of the skirt. The bottom surface mounts against a socket carried on a circuit board and is electrically coupled to a ground plane of the circuit board. The socket substantially surrounds the microprocessor in at least two dimensions (e.g. length and width). A shielding structure is formed at least partly by the heat sink, the socket and the ground plane.

Abstract: Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.

Abstract: The present application describes an apparatus and method for dispensing interface materials for electronic packages. According to some embodiments, a cooling radiator is attached using adhesive interface material (e.g., on the perimeter, edges, distributed spots or the like) to an electronic package. After the adhesive interface material cures, the thermal interface material is dispensed (e.g., thorough an opening in the cooling radiator, adhesive interface material or the like). The dispensing of the thermal interface material does not leave a gap between the adhesive interface material and thermal interface material thus providing a better thermal performance and hence, enhanced power dissipation for the electronic package.

Abstract: A heat spreader for cooling an electronic component. The heat spreader includes a thermal interface material disposed in a cavity in the body of the heat spreader. The thermal interface material is at least partially enclosed in the cavity by a surface of the electronic component or a heat sink.

Abstract: An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a heat sink with an integrally formed depending skirt, and a conductive, compressible polymer is applied to a bottom surface of the skirt. The bottom surface mounts against a socket carried on a circuit board and is electrically coupled to a ground plane of the circuit board. The socket substantially surrounds the microprocessor in at least two dimensions (e.g. length and width). A shielding structure is formed at least partly by the heat sink, the socket and the ground plane.

Abstract: In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the perimeter portion of the heat spreader is selected from material with a lower CTE than the material for the center portion of the heat spreader.

Abstract: A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.

Abstract: Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.

Abstract: In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the perimeter portion of the heat spreader is selected from material with a lower CTE than the material for the center portion of the heat spreader.

Abstract: A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Abstract: A method for reducing soft error rates in semiconductor devices includes adding an isotopically enriched 11B compound during the manufacture of a semiconductor device. Such isotopically enriched 11B compounds include orthoborates (BOR3), acyl borates (B(OCOR)3), peroxo borates (OOR)3, boronic acids (RB(OH)2), boron halides, boron hydrides, inorganic boranes, amine boranes, aminoboranes, carboranes, and borazines, where R is an alkyl group. Disclosed uses include adding between 1% to 100% of the isotopically enriched 11B compound to an underfill material in flip-chip assembly; adding between 1% to 100% of the isotopically enriched 11B compound to an encapsulent; and adding between 1% to 100% of the isotopically enriched 11B compound to an adhesive.

Abstract: A method for configuring a device's interaction with an application without using cookies. The method includes entering information that needs to be used each time a transaction with an application residing on an application server is performed and storing the information at the application server. The method also includes initiating the transaction between the device and the application server, and looking up based on a user indicator an automatic entry indicator. The then includes sending from the application server the information when the automatic entry indicator is indicative of automatic entry having been enabled.

Abstract: A method and apparatus for packaging an electronic device, such as an integrated circuit chip (8), includes an intermediate device carrier (6) with a substantially planar upper surface (16) and a plurality of bonding pads (18) for coupling the carrier to the integrated circuit chip. A ceramic ring (38) is attached to the upper surface of the device carrier and a thermally conductive cover plate (36) is attached to the ceramic ring to form an inner cavity for receiving the chip therein. The ceramic ring comprises a material with a coefficient of thermal expansion substantially similar to or as the same as the device carrier to minimize stress therebetween during thermal expansion or contraction of the package device. The thermally conductive cover plate provides a path for dissipating heat generated during electrical operations of the chip.

Abstract: A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.