Abstract: An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

Abstract: An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switche to the feedback switches to accelerate the pull up or the pull down.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down.

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down.

Abstract: A Schmitt trigger circuit includes a first inverter, second inverter, first feedback unit, and second feedback unit. The first inverter includes a PMOS transistor unit and an NMOS transistor unit which generate an internal signal by inverting an input signal based on a first feedback signal and provide the internal signal to a first node. A second inverter generates an output signal by inverting the first signal. A first feedback unit generates a first feedback signal providing a first hysteresis character to a first unit among the PMOS transistor unit and NMOS transistor unit based on a first signal of the first node. A second feedback unit generates a second feedback signal providing a second hysteresis character to a second unit among the PMOS transistor unit and NMOS transistor unit based on the output signal. The second feedback unit provides the second feedback signal to the first node.

Abstract: A Schmitt trigger circuit includes a first inverter, second inverter, first feedback unit, and second feedback unit. The first inverter includes a PMOS transistor unit and an NMOS transistor unit which generate an internal signal by inverting an input signal based on a first feedback signal and provide the internal signal to a first node. A second inverter generates an output signal by inverting the first signal. A first feedback unit generates a first feedback signal providing a first hysteresis character to a first unit among the PMOS transistor unit and NMOS transistor unit based on a first signal of the first node. A second feedback unit generates a second feedback signal providing a second hysteresis character to a second unit among the PMOS transistor unit and NMOS transistor unit based on the output signal. The second feedback unit provides the second feedback signal to the first node.

Abstract: An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.

Abstract: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Abstract: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Abstract: An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.